/***************************************************************************//**
* \file cyreg_dw.h
*
* \brief
* DW register definition header
*
* \note
* Generator version: 1.5.0.1299
* Database revision: TVIIBH4M_WW1937_for_CFR_MetalTO
*
********************************************************************************
* \copyright
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/

#ifndef _CYREG_DW_H_
#define _CYREG_DW_H_

#include "cyip_dw.h"

/**
  * \brief DW channel structure (DW_CH_STRUCT0)
  */
#define CYREG_DW0_CH_STRUCT0_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288000UL)
#define CYREG_DW0_CH_STRUCT0_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288004UL)
#define CYREG_DW0_CH_STRUCT0_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288008UL)
#define CYREG_DW0_CH_STRUCT0_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028800CUL)
#define CYREG_DW0_CH_STRUCT0_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288010UL)
#define CYREG_DW0_CH_STRUCT0_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288014UL)
#define CYREG_DW0_CH_STRUCT0_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288018UL)
#define CYREG_DW0_CH_STRUCT0_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028801CUL)
#define CYREG_DW0_CH_STRUCT0_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288020UL)
#define CYREG_DW0_CH_STRUCT0_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288024UL)
#define CYREG_DW0_CH_STRUCT0_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288028UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT1)
  */
#define CYREG_DW0_CH_STRUCT1_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288040UL)
#define CYREG_DW0_CH_STRUCT1_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288044UL)
#define CYREG_DW0_CH_STRUCT1_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288048UL)
#define CYREG_DW0_CH_STRUCT1_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028804CUL)
#define CYREG_DW0_CH_STRUCT1_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288050UL)
#define CYREG_DW0_CH_STRUCT1_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288054UL)
#define CYREG_DW0_CH_STRUCT1_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288058UL)
#define CYREG_DW0_CH_STRUCT1_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028805CUL)
#define CYREG_DW0_CH_STRUCT1_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288060UL)
#define CYREG_DW0_CH_STRUCT1_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288064UL)
#define CYREG_DW0_CH_STRUCT1_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288068UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT2)
  */
#define CYREG_DW0_CH_STRUCT2_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288080UL)
#define CYREG_DW0_CH_STRUCT2_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288084UL)
#define CYREG_DW0_CH_STRUCT2_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288088UL)
#define CYREG_DW0_CH_STRUCT2_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028808CUL)
#define CYREG_DW0_CH_STRUCT2_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288090UL)
#define CYREG_DW0_CH_STRUCT2_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288094UL)
#define CYREG_DW0_CH_STRUCT2_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288098UL)
#define CYREG_DW0_CH_STRUCT2_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028809CUL)
#define CYREG_DW0_CH_STRUCT2_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402880A0UL)
#define CYREG_DW0_CH_STRUCT2_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402880A4UL)
#define CYREG_DW0_CH_STRUCT2_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402880A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT3)
  */
#define CYREG_DW0_CH_STRUCT3_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402880C0UL)
#define CYREG_DW0_CH_STRUCT3_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402880C4UL)
#define CYREG_DW0_CH_STRUCT3_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402880C8UL)
#define CYREG_DW0_CH_STRUCT3_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402880CCUL)
#define CYREG_DW0_CH_STRUCT3_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402880D0UL)
#define CYREG_DW0_CH_STRUCT3_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402880D4UL)
#define CYREG_DW0_CH_STRUCT3_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402880D8UL)
#define CYREG_DW0_CH_STRUCT3_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402880DCUL)
#define CYREG_DW0_CH_STRUCT3_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402880E0UL)
#define CYREG_DW0_CH_STRUCT3_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402880E4UL)
#define CYREG_DW0_CH_STRUCT3_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402880E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT4)
  */
#define CYREG_DW0_CH_STRUCT4_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288100UL)
#define CYREG_DW0_CH_STRUCT4_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288104UL)
#define CYREG_DW0_CH_STRUCT4_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288108UL)
#define CYREG_DW0_CH_STRUCT4_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028810CUL)
#define CYREG_DW0_CH_STRUCT4_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288110UL)
#define CYREG_DW0_CH_STRUCT4_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288114UL)
#define CYREG_DW0_CH_STRUCT4_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288118UL)
#define CYREG_DW0_CH_STRUCT4_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028811CUL)
#define CYREG_DW0_CH_STRUCT4_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288120UL)
#define CYREG_DW0_CH_STRUCT4_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288124UL)
#define CYREG_DW0_CH_STRUCT4_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288128UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT5)
  */
#define CYREG_DW0_CH_STRUCT5_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288140UL)
#define CYREG_DW0_CH_STRUCT5_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288144UL)
#define CYREG_DW0_CH_STRUCT5_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288148UL)
#define CYREG_DW0_CH_STRUCT5_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028814CUL)
#define CYREG_DW0_CH_STRUCT5_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288150UL)
#define CYREG_DW0_CH_STRUCT5_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288154UL)
#define CYREG_DW0_CH_STRUCT5_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288158UL)
#define CYREG_DW0_CH_STRUCT5_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028815CUL)
#define CYREG_DW0_CH_STRUCT5_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288160UL)
#define CYREG_DW0_CH_STRUCT5_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288164UL)
#define CYREG_DW0_CH_STRUCT5_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288168UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT6)
  */
#define CYREG_DW0_CH_STRUCT6_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288180UL)
#define CYREG_DW0_CH_STRUCT6_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288184UL)
#define CYREG_DW0_CH_STRUCT6_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288188UL)
#define CYREG_DW0_CH_STRUCT6_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028818CUL)
#define CYREG_DW0_CH_STRUCT6_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288190UL)
#define CYREG_DW0_CH_STRUCT6_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288194UL)
#define CYREG_DW0_CH_STRUCT6_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288198UL)
#define CYREG_DW0_CH_STRUCT6_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028819CUL)
#define CYREG_DW0_CH_STRUCT6_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402881A0UL)
#define CYREG_DW0_CH_STRUCT6_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402881A4UL)
#define CYREG_DW0_CH_STRUCT6_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402881A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT7)
  */
#define CYREG_DW0_CH_STRUCT7_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402881C0UL)
#define CYREG_DW0_CH_STRUCT7_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402881C4UL)
#define CYREG_DW0_CH_STRUCT7_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402881C8UL)
#define CYREG_DW0_CH_STRUCT7_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402881CCUL)
#define CYREG_DW0_CH_STRUCT7_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402881D0UL)
#define CYREG_DW0_CH_STRUCT7_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402881D4UL)
#define CYREG_DW0_CH_STRUCT7_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402881D8UL)
#define CYREG_DW0_CH_STRUCT7_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402881DCUL)
#define CYREG_DW0_CH_STRUCT7_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402881E0UL)
#define CYREG_DW0_CH_STRUCT7_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402881E4UL)
#define CYREG_DW0_CH_STRUCT7_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402881E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT8)
  */
#define CYREG_DW0_CH_STRUCT8_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288200UL)
#define CYREG_DW0_CH_STRUCT8_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288204UL)
#define CYREG_DW0_CH_STRUCT8_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288208UL)
#define CYREG_DW0_CH_STRUCT8_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028820CUL)
#define CYREG_DW0_CH_STRUCT8_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288210UL)
#define CYREG_DW0_CH_STRUCT8_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288214UL)
#define CYREG_DW0_CH_STRUCT8_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288218UL)
#define CYREG_DW0_CH_STRUCT8_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028821CUL)
#define CYREG_DW0_CH_STRUCT8_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288220UL)
#define CYREG_DW0_CH_STRUCT8_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288224UL)
#define CYREG_DW0_CH_STRUCT8_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288228UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT9)
  */
#define CYREG_DW0_CH_STRUCT9_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288240UL)
#define CYREG_DW0_CH_STRUCT9_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288244UL)
#define CYREG_DW0_CH_STRUCT9_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288248UL)
#define CYREG_DW0_CH_STRUCT9_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028824CUL)
#define CYREG_DW0_CH_STRUCT9_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288250UL)
#define CYREG_DW0_CH_STRUCT9_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288254UL)
#define CYREG_DW0_CH_STRUCT9_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288258UL)
#define CYREG_DW0_CH_STRUCT9_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028825CUL)
#define CYREG_DW0_CH_STRUCT9_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288260UL)
#define CYREG_DW0_CH_STRUCT9_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288264UL)
#define CYREG_DW0_CH_STRUCT9_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288268UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT10)
  */
#define CYREG_DW0_CH_STRUCT10_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288280UL)
#define CYREG_DW0_CH_STRUCT10_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288284UL)
#define CYREG_DW0_CH_STRUCT10_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288288UL)
#define CYREG_DW0_CH_STRUCT10_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028828CUL)
#define CYREG_DW0_CH_STRUCT10_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288290UL)
#define CYREG_DW0_CH_STRUCT10_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288294UL)
#define CYREG_DW0_CH_STRUCT10_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288298UL)
#define CYREG_DW0_CH_STRUCT10_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028829CUL)
#define CYREG_DW0_CH_STRUCT10_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402882A0UL)
#define CYREG_DW0_CH_STRUCT10_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402882A4UL)
#define CYREG_DW0_CH_STRUCT10_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402882A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT11)
  */
#define CYREG_DW0_CH_STRUCT11_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402882C0UL)
#define CYREG_DW0_CH_STRUCT11_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402882C4UL)
#define CYREG_DW0_CH_STRUCT11_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402882C8UL)
#define CYREG_DW0_CH_STRUCT11_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402882CCUL)
#define CYREG_DW0_CH_STRUCT11_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402882D0UL)
#define CYREG_DW0_CH_STRUCT11_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402882D4UL)
#define CYREG_DW0_CH_STRUCT11_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402882D8UL)
#define CYREG_DW0_CH_STRUCT11_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402882DCUL)
#define CYREG_DW0_CH_STRUCT11_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402882E0UL)
#define CYREG_DW0_CH_STRUCT11_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402882E4UL)
#define CYREG_DW0_CH_STRUCT11_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402882E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT12)
  */
#define CYREG_DW0_CH_STRUCT12_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288300UL)
#define CYREG_DW0_CH_STRUCT12_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288304UL)
#define CYREG_DW0_CH_STRUCT12_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288308UL)
#define CYREG_DW0_CH_STRUCT12_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028830CUL)
#define CYREG_DW0_CH_STRUCT12_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288310UL)
#define CYREG_DW0_CH_STRUCT12_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288314UL)
#define CYREG_DW0_CH_STRUCT12_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288318UL)
#define CYREG_DW0_CH_STRUCT12_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028831CUL)
#define CYREG_DW0_CH_STRUCT12_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288320UL)
#define CYREG_DW0_CH_STRUCT12_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288324UL)
#define CYREG_DW0_CH_STRUCT12_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288328UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT13)
  */
#define CYREG_DW0_CH_STRUCT13_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288340UL)
#define CYREG_DW0_CH_STRUCT13_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288344UL)
#define CYREG_DW0_CH_STRUCT13_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288348UL)
#define CYREG_DW0_CH_STRUCT13_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028834CUL)
#define CYREG_DW0_CH_STRUCT13_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288350UL)
#define CYREG_DW0_CH_STRUCT13_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288354UL)
#define CYREG_DW0_CH_STRUCT13_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288358UL)
#define CYREG_DW0_CH_STRUCT13_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028835CUL)
#define CYREG_DW0_CH_STRUCT13_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288360UL)
#define CYREG_DW0_CH_STRUCT13_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288364UL)
#define CYREG_DW0_CH_STRUCT13_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288368UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT14)
  */
#define CYREG_DW0_CH_STRUCT14_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288380UL)
#define CYREG_DW0_CH_STRUCT14_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288384UL)
#define CYREG_DW0_CH_STRUCT14_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288388UL)
#define CYREG_DW0_CH_STRUCT14_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028838CUL)
#define CYREG_DW0_CH_STRUCT14_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288390UL)
#define CYREG_DW0_CH_STRUCT14_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288394UL)
#define CYREG_DW0_CH_STRUCT14_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288398UL)
#define CYREG_DW0_CH_STRUCT14_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028839CUL)
#define CYREG_DW0_CH_STRUCT14_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402883A0UL)
#define CYREG_DW0_CH_STRUCT14_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402883A4UL)
#define CYREG_DW0_CH_STRUCT14_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402883A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT15)
  */
#define CYREG_DW0_CH_STRUCT15_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402883C0UL)
#define CYREG_DW0_CH_STRUCT15_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402883C4UL)
#define CYREG_DW0_CH_STRUCT15_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402883C8UL)
#define CYREG_DW0_CH_STRUCT15_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402883CCUL)
#define CYREG_DW0_CH_STRUCT15_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402883D0UL)
#define CYREG_DW0_CH_STRUCT15_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402883D4UL)
#define CYREG_DW0_CH_STRUCT15_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402883D8UL)
#define CYREG_DW0_CH_STRUCT15_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402883DCUL)
#define CYREG_DW0_CH_STRUCT15_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402883E0UL)
#define CYREG_DW0_CH_STRUCT15_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402883E4UL)
#define CYREG_DW0_CH_STRUCT15_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402883E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT16)
  */
#define CYREG_DW0_CH_STRUCT16_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288400UL)
#define CYREG_DW0_CH_STRUCT16_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288404UL)
#define CYREG_DW0_CH_STRUCT16_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288408UL)
#define CYREG_DW0_CH_STRUCT16_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028840CUL)
#define CYREG_DW0_CH_STRUCT16_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288410UL)
#define CYREG_DW0_CH_STRUCT16_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288414UL)
#define CYREG_DW0_CH_STRUCT16_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288418UL)
#define CYREG_DW0_CH_STRUCT16_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028841CUL)
#define CYREG_DW0_CH_STRUCT16_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288420UL)
#define CYREG_DW0_CH_STRUCT16_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288424UL)
#define CYREG_DW0_CH_STRUCT16_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288428UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT17)
  */
#define CYREG_DW0_CH_STRUCT17_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288440UL)
#define CYREG_DW0_CH_STRUCT17_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288444UL)
#define CYREG_DW0_CH_STRUCT17_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288448UL)
#define CYREG_DW0_CH_STRUCT17_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028844CUL)
#define CYREG_DW0_CH_STRUCT17_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288450UL)
#define CYREG_DW0_CH_STRUCT17_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288454UL)
#define CYREG_DW0_CH_STRUCT17_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288458UL)
#define CYREG_DW0_CH_STRUCT17_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028845CUL)
#define CYREG_DW0_CH_STRUCT17_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288460UL)
#define CYREG_DW0_CH_STRUCT17_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288464UL)
#define CYREG_DW0_CH_STRUCT17_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288468UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT18)
  */
#define CYREG_DW0_CH_STRUCT18_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288480UL)
#define CYREG_DW0_CH_STRUCT18_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288484UL)
#define CYREG_DW0_CH_STRUCT18_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288488UL)
#define CYREG_DW0_CH_STRUCT18_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028848CUL)
#define CYREG_DW0_CH_STRUCT18_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288490UL)
#define CYREG_DW0_CH_STRUCT18_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288494UL)
#define CYREG_DW0_CH_STRUCT18_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288498UL)
#define CYREG_DW0_CH_STRUCT18_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028849CUL)
#define CYREG_DW0_CH_STRUCT18_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402884A0UL)
#define CYREG_DW0_CH_STRUCT18_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402884A4UL)
#define CYREG_DW0_CH_STRUCT18_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402884A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT19)
  */
#define CYREG_DW0_CH_STRUCT19_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402884C0UL)
#define CYREG_DW0_CH_STRUCT19_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402884C4UL)
#define CYREG_DW0_CH_STRUCT19_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402884C8UL)
#define CYREG_DW0_CH_STRUCT19_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402884CCUL)
#define CYREG_DW0_CH_STRUCT19_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402884D0UL)
#define CYREG_DW0_CH_STRUCT19_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402884D4UL)
#define CYREG_DW0_CH_STRUCT19_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402884D8UL)
#define CYREG_DW0_CH_STRUCT19_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402884DCUL)
#define CYREG_DW0_CH_STRUCT19_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402884E0UL)
#define CYREG_DW0_CH_STRUCT19_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402884E4UL)
#define CYREG_DW0_CH_STRUCT19_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402884E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT20)
  */
#define CYREG_DW0_CH_STRUCT20_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288500UL)
#define CYREG_DW0_CH_STRUCT20_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288504UL)
#define CYREG_DW0_CH_STRUCT20_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288508UL)
#define CYREG_DW0_CH_STRUCT20_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028850CUL)
#define CYREG_DW0_CH_STRUCT20_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288510UL)
#define CYREG_DW0_CH_STRUCT20_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288514UL)
#define CYREG_DW0_CH_STRUCT20_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288518UL)
#define CYREG_DW0_CH_STRUCT20_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028851CUL)
#define CYREG_DW0_CH_STRUCT20_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288520UL)
#define CYREG_DW0_CH_STRUCT20_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288524UL)
#define CYREG_DW0_CH_STRUCT20_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288528UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT21)
  */
#define CYREG_DW0_CH_STRUCT21_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288540UL)
#define CYREG_DW0_CH_STRUCT21_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288544UL)
#define CYREG_DW0_CH_STRUCT21_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288548UL)
#define CYREG_DW0_CH_STRUCT21_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028854CUL)
#define CYREG_DW0_CH_STRUCT21_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288550UL)
#define CYREG_DW0_CH_STRUCT21_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288554UL)
#define CYREG_DW0_CH_STRUCT21_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288558UL)
#define CYREG_DW0_CH_STRUCT21_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028855CUL)
#define CYREG_DW0_CH_STRUCT21_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288560UL)
#define CYREG_DW0_CH_STRUCT21_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288564UL)
#define CYREG_DW0_CH_STRUCT21_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288568UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT22)
  */
#define CYREG_DW0_CH_STRUCT22_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288580UL)
#define CYREG_DW0_CH_STRUCT22_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288584UL)
#define CYREG_DW0_CH_STRUCT22_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288588UL)
#define CYREG_DW0_CH_STRUCT22_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028858CUL)
#define CYREG_DW0_CH_STRUCT22_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288590UL)
#define CYREG_DW0_CH_STRUCT22_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288594UL)
#define CYREG_DW0_CH_STRUCT22_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288598UL)
#define CYREG_DW0_CH_STRUCT22_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028859CUL)
#define CYREG_DW0_CH_STRUCT22_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402885A0UL)
#define CYREG_DW0_CH_STRUCT22_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402885A4UL)
#define CYREG_DW0_CH_STRUCT22_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402885A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT23)
  */
#define CYREG_DW0_CH_STRUCT23_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402885C0UL)
#define CYREG_DW0_CH_STRUCT23_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402885C4UL)
#define CYREG_DW0_CH_STRUCT23_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402885C8UL)
#define CYREG_DW0_CH_STRUCT23_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402885CCUL)
#define CYREG_DW0_CH_STRUCT23_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402885D0UL)
#define CYREG_DW0_CH_STRUCT23_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402885D4UL)
#define CYREG_DW0_CH_STRUCT23_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402885D8UL)
#define CYREG_DW0_CH_STRUCT23_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402885DCUL)
#define CYREG_DW0_CH_STRUCT23_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402885E0UL)
#define CYREG_DW0_CH_STRUCT23_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402885E4UL)
#define CYREG_DW0_CH_STRUCT23_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402885E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT24)
  */
#define CYREG_DW0_CH_STRUCT24_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288600UL)
#define CYREG_DW0_CH_STRUCT24_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288604UL)
#define CYREG_DW0_CH_STRUCT24_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288608UL)
#define CYREG_DW0_CH_STRUCT24_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028860CUL)
#define CYREG_DW0_CH_STRUCT24_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288610UL)
#define CYREG_DW0_CH_STRUCT24_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288614UL)
#define CYREG_DW0_CH_STRUCT24_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288618UL)
#define CYREG_DW0_CH_STRUCT24_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028861CUL)
#define CYREG_DW0_CH_STRUCT24_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288620UL)
#define CYREG_DW0_CH_STRUCT24_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288624UL)
#define CYREG_DW0_CH_STRUCT24_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288628UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT25)
  */
#define CYREG_DW0_CH_STRUCT25_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288640UL)
#define CYREG_DW0_CH_STRUCT25_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288644UL)
#define CYREG_DW0_CH_STRUCT25_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288648UL)
#define CYREG_DW0_CH_STRUCT25_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028864CUL)
#define CYREG_DW0_CH_STRUCT25_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288650UL)
#define CYREG_DW0_CH_STRUCT25_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288654UL)
#define CYREG_DW0_CH_STRUCT25_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288658UL)
#define CYREG_DW0_CH_STRUCT25_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028865CUL)
#define CYREG_DW0_CH_STRUCT25_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288660UL)
#define CYREG_DW0_CH_STRUCT25_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288664UL)
#define CYREG_DW0_CH_STRUCT25_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288668UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT26)
  */
#define CYREG_DW0_CH_STRUCT26_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288680UL)
#define CYREG_DW0_CH_STRUCT26_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288684UL)
#define CYREG_DW0_CH_STRUCT26_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288688UL)
#define CYREG_DW0_CH_STRUCT26_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028868CUL)
#define CYREG_DW0_CH_STRUCT26_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288690UL)
#define CYREG_DW0_CH_STRUCT26_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288694UL)
#define CYREG_DW0_CH_STRUCT26_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288698UL)
#define CYREG_DW0_CH_STRUCT26_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028869CUL)
#define CYREG_DW0_CH_STRUCT26_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402886A0UL)
#define CYREG_DW0_CH_STRUCT26_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402886A4UL)
#define CYREG_DW0_CH_STRUCT26_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402886A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT27)
  */
#define CYREG_DW0_CH_STRUCT27_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402886C0UL)
#define CYREG_DW0_CH_STRUCT27_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402886C4UL)
#define CYREG_DW0_CH_STRUCT27_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402886C8UL)
#define CYREG_DW0_CH_STRUCT27_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402886CCUL)
#define CYREG_DW0_CH_STRUCT27_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402886D0UL)
#define CYREG_DW0_CH_STRUCT27_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402886D4UL)
#define CYREG_DW0_CH_STRUCT27_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402886D8UL)
#define CYREG_DW0_CH_STRUCT27_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402886DCUL)
#define CYREG_DW0_CH_STRUCT27_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402886E0UL)
#define CYREG_DW0_CH_STRUCT27_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402886E4UL)
#define CYREG_DW0_CH_STRUCT27_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402886E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT28)
  */
#define CYREG_DW0_CH_STRUCT28_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288700UL)
#define CYREG_DW0_CH_STRUCT28_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288704UL)
#define CYREG_DW0_CH_STRUCT28_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288708UL)
#define CYREG_DW0_CH_STRUCT28_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028870CUL)
#define CYREG_DW0_CH_STRUCT28_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288710UL)
#define CYREG_DW0_CH_STRUCT28_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288714UL)
#define CYREG_DW0_CH_STRUCT28_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288718UL)
#define CYREG_DW0_CH_STRUCT28_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028871CUL)
#define CYREG_DW0_CH_STRUCT28_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288720UL)
#define CYREG_DW0_CH_STRUCT28_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288724UL)
#define CYREG_DW0_CH_STRUCT28_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288728UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT29)
  */
#define CYREG_DW0_CH_STRUCT29_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288740UL)
#define CYREG_DW0_CH_STRUCT29_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288744UL)
#define CYREG_DW0_CH_STRUCT29_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288748UL)
#define CYREG_DW0_CH_STRUCT29_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028874CUL)
#define CYREG_DW0_CH_STRUCT29_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288750UL)
#define CYREG_DW0_CH_STRUCT29_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288754UL)
#define CYREG_DW0_CH_STRUCT29_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288758UL)
#define CYREG_DW0_CH_STRUCT29_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028875CUL)
#define CYREG_DW0_CH_STRUCT29_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288760UL)
#define CYREG_DW0_CH_STRUCT29_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288764UL)
#define CYREG_DW0_CH_STRUCT29_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288768UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT30)
  */
#define CYREG_DW0_CH_STRUCT30_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288780UL)
#define CYREG_DW0_CH_STRUCT30_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288784UL)
#define CYREG_DW0_CH_STRUCT30_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288788UL)
#define CYREG_DW0_CH_STRUCT30_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028878CUL)
#define CYREG_DW0_CH_STRUCT30_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288790UL)
#define CYREG_DW0_CH_STRUCT30_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288794UL)
#define CYREG_DW0_CH_STRUCT30_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288798UL)
#define CYREG_DW0_CH_STRUCT30_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028879CUL)
#define CYREG_DW0_CH_STRUCT30_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402887A0UL)
#define CYREG_DW0_CH_STRUCT30_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402887A4UL)
#define CYREG_DW0_CH_STRUCT30_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402887A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT31)
  */
#define CYREG_DW0_CH_STRUCT31_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402887C0UL)
#define CYREG_DW0_CH_STRUCT31_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402887C4UL)
#define CYREG_DW0_CH_STRUCT31_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402887C8UL)
#define CYREG_DW0_CH_STRUCT31_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402887CCUL)
#define CYREG_DW0_CH_STRUCT31_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402887D0UL)
#define CYREG_DW0_CH_STRUCT31_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402887D4UL)
#define CYREG_DW0_CH_STRUCT31_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402887D8UL)
#define CYREG_DW0_CH_STRUCT31_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402887DCUL)
#define CYREG_DW0_CH_STRUCT31_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402887E0UL)
#define CYREG_DW0_CH_STRUCT31_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402887E4UL)
#define CYREG_DW0_CH_STRUCT31_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402887E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT32)
  */
#define CYREG_DW0_CH_STRUCT32_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288800UL)
#define CYREG_DW0_CH_STRUCT32_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288804UL)
#define CYREG_DW0_CH_STRUCT32_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288808UL)
#define CYREG_DW0_CH_STRUCT32_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028880CUL)
#define CYREG_DW0_CH_STRUCT32_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288810UL)
#define CYREG_DW0_CH_STRUCT32_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288814UL)
#define CYREG_DW0_CH_STRUCT32_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288818UL)
#define CYREG_DW0_CH_STRUCT32_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028881CUL)
#define CYREG_DW0_CH_STRUCT32_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288820UL)
#define CYREG_DW0_CH_STRUCT32_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288824UL)
#define CYREG_DW0_CH_STRUCT32_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288828UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT33)
  */
#define CYREG_DW0_CH_STRUCT33_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288840UL)
#define CYREG_DW0_CH_STRUCT33_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288844UL)
#define CYREG_DW0_CH_STRUCT33_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288848UL)
#define CYREG_DW0_CH_STRUCT33_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028884CUL)
#define CYREG_DW0_CH_STRUCT33_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288850UL)
#define CYREG_DW0_CH_STRUCT33_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288854UL)
#define CYREG_DW0_CH_STRUCT33_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288858UL)
#define CYREG_DW0_CH_STRUCT33_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028885CUL)
#define CYREG_DW0_CH_STRUCT33_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288860UL)
#define CYREG_DW0_CH_STRUCT33_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288864UL)
#define CYREG_DW0_CH_STRUCT33_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288868UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT34)
  */
#define CYREG_DW0_CH_STRUCT34_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288880UL)
#define CYREG_DW0_CH_STRUCT34_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288884UL)
#define CYREG_DW0_CH_STRUCT34_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288888UL)
#define CYREG_DW0_CH_STRUCT34_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028888CUL)
#define CYREG_DW0_CH_STRUCT34_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288890UL)
#define CYREG_DW0_CH_STRUCT34_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288894UL)
#define CYREG_DW0_CH_STRUCT34_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288898UL)
#define CYREG_DW0_CH_STRUCT34_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028889CUL)
#define CYREG_DW0_CH_STRUCT34_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402888A0UL)
#define CYREG_DW0_CH_STRUCT34_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402888A4UL)
#define CYREG_DW0_CH_STRUCT34_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402888A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT35)
  */
#define CYREG_DW0_CH_STRUCT35_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402888C0UL)
#define CYREG_DW0_CH_STRUCT35_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402888C4UL)
#define CYREG_DW0_CH_STRUCT35_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402888C8UL)
#define CYREG_DW0_CH_STRUCT35_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402888CCUL)
#define CYREG_DW0_CH_STRUCT35_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402888D0UL)
#define CYREG_DW0_CH_STRUCT35_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402888D4UL)
#define CYREG_DW0_CH_STRUCT35_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402888D8UL)
#define CYREG_DW0_CH_STRUCT35_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402888DCUL)
#define CYREG_DW0_CH_STRUCT35_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402888E0UL)
#define CYREG_DW0_CH_STRUCT35_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402888E4UL)
#define CYREG_DW0_CH_STRUCT35_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402888E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT36)
  */
#define CYREG_DW0_CH_STRUCT36_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288900UL)
#define CYREG_DW0_CH_STRUCT36_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288904UL)
#define CYREG_DW0_CH_STRUCT36_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288908UL)
#define CYREG_DW0_CH_STRUCT36_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028890CUL)
#define CYREG_DW0_CH_STRUCT36_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288910UL)
#define CYREG_DW0_CH_STRUCT36_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288914UL)
#define CYREG_DW0_CH_STRUCT36_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288918UL)
#define CYREG_DW0_CH_STRUCT36_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028891CUL)
#define CYREG_DW0_CH_STRUCT36_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288920UL)
#define CYREG_DW0_CH_STRUCT36_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288924UL)
#define CYREG_DW0_CH_STRUCT36_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288928UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT37)
  */
#define CYREG_DW0_CH_STRUCT37_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288940UL)
#define CYREG_DW0_CH_STRUCT37_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288944UL)
#define CYREG_DW0_CH_STRUCT37_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288948UL)
#define CYREG_DW0_CH_STRUCT37_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028894CUL)
#define CYREG_DW0_CH_STRUCT37_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288950UL)
#define CYREG_DW0_CH_STRUCT37_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288954UL)
#define CYREG_DW0_CH_STRUCT37_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288958UL)
#define CYREG_DW0_CH_STRUCT37_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028895CUL)
#define CYREG_DW0_CH_STRUCT37_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288960UL)
#define CYREG_DW0_CH_STRUCT37_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288964UL)
#define CYREG_DW0_CH_STRUCT37_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288968UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT38)
  */
#define CYREG_DW0_CH_STRUCT38_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288980UL)
#define CYREG_DW0_CH_STRUCT38_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288984UL)
#define CYREG_DW0_CH_STRUCT38_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288988UL)
#define CYREG_DW0_CH_STRUCT38_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028898CUL)
#define CYREG_DW0_CH_STRUCT38_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288990UL)
#define CYREG_DW0_CH_STRUCT38_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288994UL)
#define CYREG_DW0_CH_STRUCT38_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288998UL)
#define CYREG_DW0_CH_STRUCT38_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028899CUL)
#define CYREG_DW0_CH_STRUCT38_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402889A0UL)
#define CYREG_DW0_CH_STRUCT38_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402889A4UL)
#define CYREG_DW0_CH_STRUCT38_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402889A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT39)
  */
#define CYREG_DW0_CH_STRUCT39_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402889C0UL)
#define CYREG_DW0_CH_STRUCT39_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402889C4UL)
#define CYREG_DW0_CH_STRUCT39_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402889C8UL)
#define CYREG_DW0_CH_STRUCT39_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402889CCUL)
#define CYREG_DW0_CH_STRUCT39_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402889D0UL)
#define CYREG_DW0_CH_STRUCT39_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402889D4UL)
#define CYREG_DW0_CH_STRUCT39_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402889D8UL)
#define CYREG_DW0_CH_STRUCT39_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402889DCUL)
#define CYREG_DW0_CH_STRUCT39_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402889E0UL)
#define CYREG_DW0_CH_STRUCT39_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402889E4UL)
#define CYREG_DW0_CH_STRUCT39_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402889E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT40)
  */
#define CYREG_DW0_CH_STRUCT40_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288A00UL)
#define CYREG_DW0_CH_STRUCT40_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288A04UL)
#define CYREG_DW0_CH_STRUCT40_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288A08UL)
#define CYREG_DW0_CH_STRUCT40_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288A0CUL)
#define CYREG_DW0_CH_STRUCT40_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288A10UL)
#define CYREG_DW0_CH_STRUCT40_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288A14UL)
#define CYREG_DW0_CH_STRUCT40_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288A18UL)
#define CYREG_DW0_CH_STRUCT40_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288A1CUL)
#define CYREG_DW0_CH_STRUCT40_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288A20UL)
#define CYREG_DW0_CH_STRUCT40_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288A24UL)
#define CYREG_DW0_CH_STRUCT40_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288A28UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT41)
  */
#define CYREG_DW0_CH_STRUCT41_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288A40UL)
#define CYREG_DW0_CH_STRUCT41_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288A44UL)
#define CYREG_DW0_CH_STRUCT41_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288A48UL)
#define CYREG_DW0_CH_STRUCT41_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288A4CUL)
#define CYREG_DW0_CH_STRUCT41_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288A50UL)
#define CYREG_DW0_CH_STRUCT41_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288A54UL)
#define CYREG_DW0_CH_STRUCT41_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288A58UL)
#define CYREG_DW0_CH_STRUCT41_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288A5CUL)
#define CYREG_DW0_CH_STRUCT41_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288A60UL)
#define CYREG_DW0_CH_STRUCT41_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288A64UL)
#define CYREG_DW0_CH_STRUCT41_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288A68UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT42)
  */
#define CYREG_DW0_CH_STRUCT42_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288A80UL)
#define CYREG_DW0_CH_STRUCT42_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288A84UL)
#define CYREG_DW0_CH_STRUCT42_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288A88UL)
#define CYREG_DW0_CH_STRUCT42_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288A8CUL)
#define CYREG_DW0_CH_STRUCT42_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288A90UL)
#define CYREG_DW0_CH_STRUCT42_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288A94UL)
#define CYREG_DW0_CH_STRUCT42_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288A98UL)
#define CYREG_DW0_CH_STRUCT42_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288A9CUL)
#define CYREG_DW0_CH_STRUCT42_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288AA0UL)
#define CYREG_DW0_CH_STRUCT42_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288AA4UL)
#define CYREG_DW0_CH_STRUCT42_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288AA8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT43)
  */
#define CYREG_DW0_CH_STRUCT43_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288AC0UL)
#define CYREG_DW0_CH_STRUCT43_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288AC4UL)
#define CYREG_DW0_CH_STRUCT43_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288AC8UL)
#define CYREG_DW0_CH_STRUCT43_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288ACCUL)
#define CYREG_DW0_CH_STRUCT43_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288AD0UL)
#define CYREG_DW0_CH_STRUCT43_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288AD4UL)
#define CYREG_DW0_CH_STRUCT43_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288AD8UL)
#define CYREG_DW0_CH_STRUCT43_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288ADCUL)
#define CYREG_DW0_CH_STRUCT43_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288AE0UL)
#define CYREG_DW0_CH_STRUCT43_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288AE4UL)
#define CYREG_DW0_CH_STRUCT43_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288AE8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT44)
  */
#define CYREG_DW0_CH_STRUCT44_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288B00UL)
#define CYREG_DW0_CH_STRUCT44_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288B04UL)
#define CYREG_DW0_CH_STRUCT44_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288B08UL)
#define CYREG_DW0_CH_STRUCT44_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288B0CUL)
#define CYREG_DW0_CH_STRUCT44_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288B10UL)
#define CYREG_DW0_CH_STRUCT44_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288B14UL)
#define CYREG_DW0_CH_STRUCT44_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288B18UL)
#define CYREG_DW0_CH_STRUCT44_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288B1CUL)
#define CYREG_DW0_CH_STRUCT44_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288B20UL)
#define CYREG_DW0_CH_STRUCT44_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288B24UL)
#define CYREG_DW0_CH_STRUCT44_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288B28UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT45)
  */
#define CYREG_DW0_CH_STRUCT45_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288B40UL)
#define CYREG_DW0_CH_STRUCT45_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288B44UL)
#define CYREG_DW0_CH_STRUCT45_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288B48UL)
#define CYREG_DW0_CH_STRUCT45_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288B4CUL)
#define CYREG_DW0_CH_STRUCT45_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288B50UL)
#define CYREG_DW0_CH_STRUCT45_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288B54UL)
#define CYREG_DW0_CH_STRUCT45_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288B58UL)
#define CYREG_DW0_CH_STRUCT45_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288B5CUL)
#define CYREG_DW0_CH_STRUCT45_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288B60UL)
#define CYREG_DW0_CH_STRUCT45_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288B64UL)
#define CYREG_DW0_CH_STRUCT45_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288B68UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT46)
  */
#define CYREG_DW0_CH_STRUCT46_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288B80UL)
#define CYREG_DW0_CH_STRUCT46_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288B84UL)
#define CYREG_DW0_CH_STRUCT46_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288B88UL)
#define CYREG_DW0_CH_STRUCT46_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288B8CUL)
#define CYREG_DW0_CH_STRUCT46_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288B90UL)
#define CYREG_DW0_CH_STRUCT46_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288B94UL)
#define CYREG_DW0_CH_STRUCT46_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288B98UL)
#define CYREG_DW0_CH_STRUCT46_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288B9CUL)
#define CYREG_DW0_CH_STRUCT46_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288BA0UL)
#define CYREG_DW0_CH_STRUCT46_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288BA4UL)
#define CYREG_DW0_CH_STRUCT46_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288BA8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT47)
  */
#define CYREG_DW0_CH_STRUCT47_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288BC0UL)
#define CYREG_DW0_CH_STRUCT47_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288BC4UL)
#define CYREG_DW0_CH_STRUCT47_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288BC8UL)
#define CYREG_DW0_CH_STRUCT47_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288BCCUL)
#define CYREG_DW0_CH_STRUCT47_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288BD0UL)
#define CYREG_DW0_CH_STRUCT47_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288BD4UL)
#define CYREG_DW0_CH_STRUCT47_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288BD8UL)
#define CYREG_DW0_CH_STRUCT47_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288BDCUL)
#define CYREG_DW0_CH_STRUCT47_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288BE0UL)
#define CYREG_DW0_CH_STRUCT47_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288BE4UL)
#define CYREG_DW0_CH_STRUCT47_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288BE8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT48)
  */
#define CYREG_DW0_CH_STRUCT48_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288C00UL)
#define CYREG_DW0_CH_STRUCT48_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288C04UL)
#define CYREG_DW0_CH_STRUCT48_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288C08UL)
#define CYREG_DW0_CH_STRUCT48_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288C0CUL)
#define CYREG_DW0_CH_STRUCT48_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288C10UL)
#define CYREG_DW0_CH_STRUCT48_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288C14UL)
#define CYREG_DW0_CH_STRUCT48_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288C18UL)
#define CYREG_DW0_CH_STRUCT48_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288C1CUL)
#define CYREG_DW0_CH_STRUCT48_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288C20UL)
#define CYREG_DW0_CH_STRUCT48_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288C24UL)
#define CYREG_DW0_CH_STRUCT48_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288C28UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT49)
  */
#define CYREG_DW0_CH_STRUCT49_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288C40UL)
#define CYREG_DW0_CH_STRUCT49_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288C44UL)
#define CYREG_DW0_CH_STRUCT49_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288C48UL)
#define CYREG_DW0_CH_STRUCT49_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288C4CUL)
#define CYREG_DW0_CH_STRUCT49_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288C50UL)
#define CYREG_DW0_CH_STRUCT49_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288C54UL)
#define CYREG_DW0_CH_STRUCT49_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288C58UL)
#define CYREG_DW0_CH_STRUCT49_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288C5CUL)
#define CYREG_DW0_CH_STRUCT49_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288C60UL)
#define CYREG_DW0_CH_STRUCT49_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288C64UL)
#define CYREG_DW0_CH_STRUCT49_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288C68UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT50)
  */
#define CYREG_DW0_CH_STRUCT50_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288C80UL)
#define CYREG_DW0_CH_STRUCT50_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288C84UL)
#define CYREG_DW0_CH_STRUCT50_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288C88UL)
#define CYREG_DW0_CH_STRUCT50_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288C8CUL)
#define CYREG_DW0_CH_STRUCT50_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288C90UL)
#define CYREG_DW0_CH_STRUCT50_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288C94UL)
#define CYREG_DW0_CH_STRUCT50_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288C98UL)
#define CYREG_DW0_CH_STRUCT50_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288C9CUL)
#define CYREG_DW0_CH_STRUCT50_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288CA0UL)
#define CYREG_DW0_CH_STRUCT50_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288CA4UL)
#define CYREG_DW0_CH_STRUCT50_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288CA8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT51)
  */
#define CYREG_DW0_CH_STRUCT51_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288CC0UL)
#define CYREG_DW0_CH_STRUCT51_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288CC4UL)
#define CYREG_DW0_CH_STRUCT51_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288CC8UL)
#define CYREG_DW0_CH_STRUCT51_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288CCCUL)
#define CYREG_DW0_CH_STRUCT51_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288CD0UL)
#define CYREG_DW0_CH_STRUCT51_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288CD4UL)
#define CYREG_DW0_CH_STRUCT51_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288CD8UL)
#define CYREG_DW0_CH_STRUCT51_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288CDCUL)
#define CYREG_DW0_CH_STRUCT51_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288CE0UL)
#define CYREG_DW0_CH_STRUCT51_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288CE4UL)
#define CYREG_DW0_CH_STRUCT51_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288CE8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT52)
  */
#define CYREG_DW0_CH_STRUCT52_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288D00UL)
#define CYREG_DW0_CH_STRUCT52_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288D04UL)
#define CYREG_DW0_CH_STRUCT52_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288D08UL)
#define CYREG_DW0_CH_STRUCT52_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288D0CUL)
#define CYREG_DW0_CH_STRUCT52_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288D10UL)
#define CYREG_DW0_CH_STRUCT52_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288D14UL)
#define CYREG_DW0_CH_STRUCT52_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288D18UL)
#define CYREG_DW0_CH_STRUCT52_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288D1CUL)
#define CYREG_DW0_CH_STRUCT52_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288D20UL)
#define CYREG_DW0_CH_STRUCT52_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288D24UL)
#define CYREG_DW0_CH_STRUCT52_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288D28UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT53)
  */
#define CYREG_DW0_CH_STRUCT53_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288D40UL)
#define CYREG_DW0_CH_STRUCT53_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288D44UL)
#define CYREG_DW0_CH_STRUCT53_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288D48UL)
#define CYREG_DW0_CH_STRUCT53_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288D4CUL)
#define CYREG_DW0_CH_STRUCT53_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288D50UL)
#define CYREG_DW0_CH_STRUCT53_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288D54UL)
#define CYREG_DW0_CH_STRUCT53_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288D58UL)
#define CYREG_DW0_CH_STRUCT53_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288D5CUL)
#define CYREG_DW0_CH_STRUCT53_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288D60UL)
#define CYREG_DW0_CH_STRUCT53_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288D64UL)
#define CYREG_DW0_CH_STRUCT53_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288D68UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT54)
  */
#define CYREG_DW0_CH_STRUCT54_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288D80UL)
#define CYREG_DW0_CH_STRUCT54_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288D84UL)
#define CYREG_DW0_CH_STRUCT54_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288D88UL)
#define CYREG_DW0_CH_STRUCT54_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288D8CUL)
#define CYREG_DW0_CH_STRUCT54_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288D90UL)
#define CYREG_DW0_CH_STRUCT54_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288D94UL)
#define CYREG_DW0_CH_STRUCT54_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288D98UL)
#define CYREG_DW0_CH_STRUCT54_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288D9CUL)
#define CYREG_DW0_CH_STRUCT54_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288DA0UL)
#define CYREG_DW0_CH_STRUCT54_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288DA4UL)
#define CYREG_DW0_CH_STRUCT54_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288DA8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT55)
  */
#define CYREG_DW0_CH_STRUCT55_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288DC0UL)
#define CYREG_DW0_CH_STRUCT55_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288DC4UL)
#define CYREG_DW0_CH_STRUCT55_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288DC8UL)
#define CYREG_DW0_CH_STRUCT55_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288DCCUL)
#define CYREG_DW0_CH_STRUCT55_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288DD0UL)
#define CYREG_DW0_CH_STRUCT55_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288DD4UL)
#define CYREG_DW0_CH_STRUCT55_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288DD8UL)
#define CYREG_DW0_CH_STRUCT55_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288DDCUL)
#define CYREG_DW0_CH_STRUCT55_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288DE0UL)
#define CYREG_DW0_CH_STRUCT55_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288DE4UL)
#define CYREG_DW0_CH_STRUCT55_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288DE8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT56)
  */
#define CYREG_DW0_CH_STRUCT56_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288E00UL)
#define CYREG_DW0_CH_STRUCT56_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288E04UL)
#define CYREG_DW0_CH_STRUCT56_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288E08UL)
#define CYREG_DW0_CH_STRUCT56_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288E0CUL)
#define CYREG_DW0_CH_STRUCT56_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288E10UL)
#define CYREG_DW0_CH_STRUCT56_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288E14UL)
#define CYREG_DW0_CH_STRUCT56_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288E18UL)
#define CYREG_DW0_CH_STRUCT56_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288E1CUL)
#define CYREG_DW0_CH_STRUCT56_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288E20UL)
#define CYREG_DW0_CH_STRUCT56_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288E24UL)
#define CYREG_DW0_CH_STRUCT56_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288E28UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT57)
  */
#define CYREG_DW0_CH_STRUCT57_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288E40UL)
#define CYREG_DW0_CH_STRUCT57_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288E44UL)
#define CYREG_DW0_CH_STRUCT57_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288E48UL)
#define CYREG_DW0_CH_STRUCT57_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288E4CUL)
#define CYREG_DW0_CH_STRUCT57_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288E50UL)
#define CYREG_DW0_CH_STRUCT57_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288E54UL)
#define CYREG_DW0_CH_STRUCT57_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288E58UL)
#define CYREG_DW0_CH_STRUCT57_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288E5CUL)
#define CYREG_DW0_CH_STRUCT57_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288E60UL)
#define CYREG_DW0_CH_STRUCT57_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288E64UL)
#define CYREG_DW0_CH_STRUCT57_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288E68UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT58)
  */
#define CYREG_DW0_CH_STRUCT58_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288E80UL)
#define CYREG_DW0_CH_STRUCT58_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288E84UL)
#define CYREG_DW0_CH_STRUCT58_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288E88UL)
#define CYREG_DW0_CH_STRUCT58_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288E8CUL)
#define CYREG_DW0_CH_STRUCT58_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288E90UL)
#define CYREG_DW0_CH_STRUCT58_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288E94UL)
#define CYREG_DW0_CH_STRUCT58_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288E98UL)
#define CYREG_DW0_CH_STRUCT58_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288E9CUL)
#define CYREG_DW0_CH_STRUCT58_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288EA0UL)
#define CYREG_DW0_CH_STRUCT58_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288EA4UL)
#define CYREG_DW0_CH_STRUCT58_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288EA8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT59)
  */
#define CYREG_DW0_CH_STRUCT59_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288EC0UL)
#define CYREG_DW0_CH_STRUCT59_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288EC4UL)
#define CYREG_DW0_CH_STRUCT59_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288EC8UL)
#define CYREG_DW0_CH_STRUCT59_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288ECCUL)
#define CYREG_DW0_CH_STRUCT59_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288ED0UL)
#define CYREG_DW0_CH_STRUCT59_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288ED4UL)
#define CYREG_DW0_CH_STRUCT59_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288ED8UL)
#define CYREG_DW0_CH_STRUCT59_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288EDCUL)
#define CYREG_DW0_CH_STRUCT59_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288EE0UL)
#define CYREG_DW0_CH_STRUCT59_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288EE4UL)
#define CYREG_DW0_CH_STRUCT59_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288EE8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT60)
  */
#define CYREG_DW0_CH_STRUCT60_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288F00UL)
#define CYREG_DW0_CH_STRUCT60_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288F04UL)
#define CYREG_DW0_CH_STRUCT60_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288F08UL)
#define CYREG_DW0_CH_STRUCT60_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288F0CUL)
#define CYREG_DW0_CH_STRUCT60_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288F10UL)
#define CYREG_DW0_CH_STRUCT60_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288F14UL)
#define CYREG_DW0_CH_STRUCT60_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288F18UL)
#define CYREG_DW0_CH_STRUCT60_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288F1CUL)
#define CYREG_DW0_CH_STRUCT60_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288F20UL)
#define CYREG_DW0_CH_STRUCT60_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288F24UL)
#define CYREG_DW0_CH_STRUCT60_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288F28UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT61)
  */
#define CYREG_DW0_CH_STRUCT61_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288F40UL)
#define CYREG_DW0_CH_STRUCT61_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288F44UL)
#define CYREG_DW0_CH_STRUCT61_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288F48UL)
#define CYREG_DW0_CH_STRUCT61_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288F4CUL)
#define CYREG_DW0_CH_STRUCT61_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288F50UL)
#define CYREG_DW0_CH_STRUCT61_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288F54UL)
#define CYREG_DW0_CH_STRUCT61_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288F58UL)
#define CYREG_DW0_CH_STRUCT61_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288F5CUL)
#define CYREG_DW0_CH_STRUCT61_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288F60UL)
#define CYREG_DW0_CH_STRUCT61_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288F64UL)
#define CYREG_DW0_CH_STRUCT61_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288F68UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT62)
  */
#define CYREG_DW0_CH_STRUCT62_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288F80UL)
#define CYREG_DW0_CH_STRUCT62_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288F84UL)
#define CYREG_DW0_CH_STRUCT62_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288F88UL)
#define CYREG_DW0_CH_STRUCT62_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288F8CUL)
#define CYREG_DW0_CH_STRUCT62_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288F90UL)
#define CYREG_DW0_CH_STRUCT62_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288F94UL)
#define CYREG_DW0_CH_STRUCT62_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288F98UL)
#define CYREG_DW0_CH_STRUCT62_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288F9CUL)
#define CYREG_DW0_CH_STRUCT62_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288FA0UL)
#define CYREG_DW0_CH_STRUCT62_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288FA4UL)
#define CYREG_DW0_CH_STRUCT62_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288FA8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT63)
  */
#define CYREG_DW0_CH_STRUCT63_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40288FC0UL)
#define CYREG_DW0_CH_STRUCT63_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40288FC4UL)
#define CYREG_DW0_CH_STRUCT63_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40288FC8UL)
#define CYREG_DW0_CH_STRUCT63_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40288FCCUL)
#define CYREG_DW0_CH_STRUCT63_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40288FD0UL)
#define CYREG_DW0_CH_STRUCT63_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40288FD4UL)
#define CYREG_DW0_CH_STRUCT63_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40288FD8UL)
#define CYREG_DW0_CH_STRUCT63_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40288FDCUL)
#define CYREG_DW0_CH_STRUCT63_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40288FE0UL)
#define CYREG_DW0_CH_STRUCT63_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40288FE4UL)
#define CYREG_DW0_CH_STRUCT63_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40288FE8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT64)
  */
#define CYREG_DW0_CH_STRUCT64_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289000UL)
#define CYREG_DW0_CH_STRUCT64_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289004UL)
#define CYREG_DW0_CH_STRUCT64_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289008UL)
#define CYREG_DW0_CH_STRUCT64_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028900CUL)
#define CYREG_DW0_CH_STRUCT64_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289010UL)
#define CYREG_DW0_CH_STRUCT64_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289014UL)
#define CYREG_DW0_CH_STRUCT64_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289018UL)
#define CYREG_DW0_CH_STRUCT64_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028901CUL)
#define CYREG_DW0_CH_STRUCT64_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40289020UL)
#define CYREG_DW0_CH_STRUCT64_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40289024UL)
#define CYREG_DW0_CH_STRUCT64_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40289028UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT65)
  */
#define CYREG_DW0_CH_STRUCT65_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289040UL)
#define CYREG_DW0_CH_STRUCT65_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289044UL)
#define CYREG_DW0_CH_STRUCT65_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289048UL)
#define CYREG_DW0_CH_STRUCT65_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028904CUL)
#define CYREG_DW0_CH_STRUCT65_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289050UL)
#define CYREG_DW0_CH_STRUCT65_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289054UL)
#define CYREG_DW0_CH_STRUCT65_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289058UL)
#define CYREG_DW0_CH_STRUCT65_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028905CUL)
#define CYREG_DW0_CH_STRUCT65_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40289060UL)
#define CYREG_DW0_CH_STRUCT65_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40289064UL)
#define CYREG_DW0_CH_STRUCT65_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40289068UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT66)
  */
#define CYREG_DW0_CH_STRUCT66_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289080UL)
#define CYREG_DW0_CH_STRUCT66_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289084UL)
#define CYREG_DW0_CH_STRUCT66_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289088UL)
#define CYREG_DW0_CH_STRUCT66_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028908CUL)
#define CYREG_DW0_CH_STRUCT66_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289090UL)
#define CYREG_DW0_CH_STRUCT66_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289094UL)
#define CYREG_DW0_CH_STRUCT66_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289098UL)
#define CYREG_DW0_CH_STRUCT66_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028909CUL)
#define CYREG_DW0_CH_STRUCT66_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402890A0UL)
#define CYREG_DW0_CH_STRUCT66_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402890A4UL)
#define CYREG_DW0_CH_STRUCT66_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402890A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT67)
  */
#define CYREG_DW0_CH_STRUCT67_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402890C0UL)
#define CYREG_DW0_CH_STRUCT67_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402890C4UL)
#define CYREG_DW0_CH_STRUCT67_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402890C8UL)
#define CYREG_DW0_CH_STRUCT67_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402890CCUL)
#define CYREG_DW0_CH_STRUCT67_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402890D0UL)
#define CYREG_DW0_CH_STRUCT67_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402890D4UL)
#define CYREG_DW0_CH_STRUCT67_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402890D8UL)
#define CYREG_DW0_CH_STRUCT67_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402890DCUL)
#define CYREG_DW0_CH_STRUCT67_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402890E0UL)
#define CYREG_DW0_CH_STRUCT67_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402890E4UL)
#define CYREG_DW0_CH_STRUCT67_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402890E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT68)
  */
#define CYREG_DW0_CH_STRUCT68_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289100UL)
#define CYREG_DW0_CH_STRUCT68_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289104UL)
#define CYREG_DW0_CH_STRUCT68_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289108UL)
#define CYREG_DW0_CH_STRUCT68_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028910CUL)
#define CYREG_DW0_CH_STRUCT68_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289110UL)
#define CYREG_DW0_CH_STRUCT68_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289114UL)
#define CYREG_DW0_CH_STRUCT68_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289118UL)
#define CYREG_DW0_CH_STRUCT68_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028911CUL)
#define CYREG_DW0_CH_STRUCT68_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40289120UL)
#define CYREG_DW0_CH_STRUCT68_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40289124UL)
#define CYREG_DW0_CH_STRUCT68_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40289128UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT69)
  */
#define CYREG_DW0_CH_STRUCT69_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289140UL)
#define CYREG_DW0_CH_STRUCT69_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289144UL)
#define CYREG_DW0_CH_STRUCT69_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289148UL)
#define CYREG_DW0_CH_STRUCT69_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028914CUL)
#define CYREG_DW0_CH_STRUCT69_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289150UL)
#define CYREG_DW0_CH_STRUCT69_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289154UL)
#define CYREG_DW0_CH_STRUCT69_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289158UL)
#define CYREG_DW0_CH_STRUCT69_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028915CUL)
#define CYREG_DW0_CH_STRUCT69_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40289160UL)
#define CYREG_DW0_CH_STRUCT69_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40289164UL)
#define CYREG_DW0_CH_STRUCT69_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40289168UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT70)
  */
#define CYREG_DW0_CH_STRUCT70_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289180UL)
#define CYREG_DW0_CH_STRUCT70_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289184UL)
#define CYREG_DW0_CH_STRUCT70_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289188UL)
#define CYREG_DW0_CH_STRUCT70_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028918CUL)
#define CYREG_DW0_CH_STRUCT70_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289190UL)
#define CYREG_DW0_CH_STRUCT70_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289194UL)
#define CYREG_DW0_CH_STRUCT70_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289198UL)
#define CYREG_DW0_CH_STRUCT70_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028919CUL)
#define CYREG_DW0_CH_STRUCT70_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402891A0UL)
#define CYREG_DW0_CH_STRUCT70_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402891A4UL)
#define CYREG_DW0_CH_STRUCT70_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402891A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT71)
  */
#define CYREG_DW0_CH_STRUCT71_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402891C0UL)
#define CYREG_DW0_CH_STRUCT71_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402891C4UL)
#define CYREG_DW0_CH_STRUCT71_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402891C8UL)
#define CYREG_DW0_CH_STRUCT71_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402891CCUL)
#define CYREG_DW0_CH_STRUCT71_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402891D0UL)
#define CYREG_DW0_CH_STRUCT71_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402891D4UL)
#define CYREG_DW0_CH_STRUCT71_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402891D8UL)
#define CYREG_DW0_CH_STRUCT71_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402891DCUL)
#define CYREG_DW0_CH_STRUCT71_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402891E0UL)
#define CYREG_DW0_CH_STRUCT71_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402891E4UL)
#define CYREG_DW0_CH_STRUCT71_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402891E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT72)
  */
#define CYREG_DW0_CH_STRUCT72_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289200UL)
#define CYREG_DW0_CH_STRUCT72_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289204UL)
#define CYREG_DW0_CH_STRUCT72_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289208UL)
#define CYREG_DW0_CH_STRUCT72_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028920CUL)
#define CYREG_DW0_CH_STRUCT72_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289210UL)
#define CYREG_DW0_CH_STRUCT72_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289214UL)
#define CYREG_DW0_CH_STRUCT72_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289218UL)
#define CYREG_DW0_CH_STRUCT72_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028921CUL)
#define CYREG_DW0_CH_STRUCT72_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40289220UL)
#define CYREG_DW0_CH_STRUCT72_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40289224UL)
#define CYREG_DW0_CH_STRUCT72_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40289228UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT73)
  */
#define CYREG_DW0_CH_STRUCT73_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289240UL)
#define CYREG_DW0_CH_STRUCT73_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289244UL)
#define CYREG_DW0_CH_STRUCT73_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289248UL)
#define CYREG_DW0_CH_STRUCT73_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028924CUL)
#define CYREG_DW0_CH_STRUCT73_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289250UL)
#define CYREG_DW0_CH_STRUCT73_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289254UL)
#define CYREG_DW0_CH_STRUCT73_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289258UL)
#define CYREG_DW0_CH_STRUCT73_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028925CUL)
#define CYREG_DW0_CH_STRUCT73_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40289260UL)
#define CYREG_DW0_CH_STRUCT73_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40289264UL)
#define CYREG_DW0_CH_STRUCT73_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40289268UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT74)
  */
#define CYREG_DW0_CH_STRUCT74_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289280UL)
#define CYREG_DW0_CH_STRUCT74_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289284UL)
#define CYREG_DW0_CH_STRUCT74_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289288UL)
#define CYREG_DW0_CH_STRUCT74_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028928CUL)
#define CYREG_DW0_CH_STRUCT74_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289290UL)
#define CYREG_DW0_CH_STRUCT74_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289294UL)
#define CYREG_DW0_CH_STRUCT74_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289298UL)
#define CYREG_DW0_CH_STRUCT74_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028929CUL)
#define CYREG_DW0_CH_STRUCT74_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402892A0UL)
#define CYREG_DW0_CH_STRUCT74_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402892A4UL)
#define CYREG_DW0_CH_STRUCT74_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402892A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT75)
  */
#define CYREG_DW0_CH_STRUCT75_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402892C0UL)
#define CYREG_DW0_CH_STRUCT75_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402892C4UL)
#define CYREG_DW0_CH_STRUCT75_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402892C8UL)
#define CYREG_DW0_CH_STRUCT75_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402892CCUL)
#define CYREG_DW0_CH_STRUCT75_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402892D0UL)
#define CYREG_DW0_CH_STRUCT75_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402892D4UL)
#define CYREG_DW0_CH_STRUCT75_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402892D8UL)
#define CYREG_DW0_CH_STRUCT75_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402892DCUL)
#define CYREG_DW0_CH_STRUCT75_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402892E0UL)
#define CYREG_DW0_CH_STRUCT75_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402892E4UL)
#define CYREG_DW0_CH_STRUCT75_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402892E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT76)
  */
#define CYREG_DW0_CH_STRUCT76_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289300UL)
#define CYREG_DW0_CH_STRUCT76_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289304UL)
#define CYREG_DW0_CH_STRUCT76_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289308UL)
#define CYREG_DW0_CH_STRUCT76_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028930CUL)
#define CYREG_DW0_CH_STRUCT76_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289310UL)
#define CYREG_DW0_CH_STRUCT76_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289314UL)
#define CYREG_DW0_CH_STRUCT76_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289318UL)
#define CYREG_DW0_CH_STRUCT76_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028931CUL)
#define CYREG_DW0_CH_STRUCT76_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40289320UL)
#define CYREG_DW0_CH_STRUCT76_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40289324UL)
#define CYREG_DW0_CH_STRUCT76_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40289328UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT77)
  */
#define CYREG_DW0_CH_STRUCT77_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289340UL)
#define CYREG_DW0_CH_STRUCT77_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289344UL)
#define CYREG_DW0_CH_STRUCT77_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289348UL)
#define CYREG_DW0_CH_STRUCT77_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028934CUL)
#define CYREG_DW0_CH_STRUCT77_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289350UL)
#define CYREG_DW0_CH_STRUCT77_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289354UL)
#define CYREG_DW0_CH_STRUCT77_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289358UL)
#define CYREG_DW0_CH_STRUCT77_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028935CUL)
#define CYREG_DW0_CH_STRUCT77_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40289360UL)
#define CYREG_DW0_CH_STRUCT77_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40289364UL)
#define CYREG_DW0_CH_STRUCT77_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40289368UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT78)
  */
#define CYREG_DW0_CH_STRUCT78_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289380UL)
#define CYREG_DW0_CH_STRUCT78_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289384UL)
#define CYREG_DW0_CH_STRUCT78_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289388UL)
#define CYREG_DW0_CH_STRUCT78_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028938CUL)
#define CYREG_DW0_CH_STRUCT78_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289390UL)
#define CYREG_DW0_CH_STRUCT78_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289394UL)
#define CYREG_DW0_CH_STRUCT78_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289398UL)
#define CYREG_DW0_CH_STRUCT78_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028939CUL)
#define CYREG_DW0_CH_STRUCT78_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402893A0UL)
#define CYREG_DW0_CH_STRUCT78_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402893A4UL)
#define CYREG_DW0_CH_STRUCT78_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402893A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT79)
  */
#define CYREG_DW0_CH_STRUCT79_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402893C0UL)
#define CYREG_DW0_CH_STRUCT79_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402893C4UL)
#define CYREG_DW0_CH_STRUCT79_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402893C8UL)
#define CYREG_DW0_CH_STRUCT79_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402893CCUL)
#define CYREG_DW0_CH_STRUCT79_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402893D0UL)
#define CYREG_DW0_CH_STRUCT79_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402893D4UL)
#define CYREG_DW0_CH_STRUCT79_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402893D8UL)
#define CYREG_DW0_CH_STRUCT79_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402893DCUL)
#define CYREG_DW0_CH_STRUCT79_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402893E0UL)
#define CYREG_DW0_CH_STRUCT79_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402893E4UL)
#define CYREG_DW0_CH_STRUCT79_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402893E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT80)
  */
#define CYREG_DW0_CH_STRUCT80_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289400UL)
#define CYREG_DW0_CH_STRUCT80_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289404UL)
#define CYREG_DW0_CH_STRUCT80_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289408UL)
#define CYREG_DW0_CH_STRUCT80_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028940CUL)
#define CYREG_DW0_CH_STRUCT80_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289410UL)
#define CYREG_DW0_CH_STRUCT80_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289414UL)
#define CYREG_DW0_CH_STRUCT80_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289418UL)
#define CYREG_DW0_CH_STRUCT80_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028941CUL)
#define CYREG_DW0_CH_STRUCT80_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40289420UL)
#define CYREG_DW0_CH_STRUCT80_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40289424UL)
#define CYREG_DW0_CH_STRUCT80_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40289428UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT81)
  */
#define CYREG_DW0_CH_STRUCT81_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289440UL)
#define CYREG_DW0_CH_STRUCT81_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289444UL)
#define CYREG_DW0_CH_STRUCT81_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289448UL)
#define CYREG_DW0_CH_STRUCT81_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028944CUL)
#define CYREG_DW0_CH_STRUCT81_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289450UL)
#define CYREG_DW0_CH_STRUCT81_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289454UL)
#define CYREG_DW0_CH_STRUCT81_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289458UL)
#define CYREG_DW0_CH_STRUCT81_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028945CUL)
#define CYREG_DW0_CH_STRUCT81_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40289460UL)
#define CYREG_DW0_CH_STRUCT81_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40289464UL)
#define CYREG_DW0_CH_STRUCT81_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40289468UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT82)
  */
#define CYREG_DW0_CH_STRUCT82_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289480UL)
#define CYREG_DW0_CH_STRUCT82_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289484UL)
#define CYREG_DW0_CH_STRUCT82_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289488UL)
#define CYREG_DW0_CH_STRUCT82_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028948CUL)
#define CYREG_DW0_CH_STRUCT82_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289490UL)
#define CYREG_DW0_CH_STRUCT82_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289494UL)
#define CYREG_DW0_CH_STRUCT82_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289498UL)
#define CYREG_DW0_CH_STRUCT82_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028949CUL)
#define CYREG_DW0_CH_STRUCT82_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402894A0UL)
#define CYREG_DW0_CH_STRUCT82_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402894A4UL)
#define CYREG_DW0_CH_STRUCT82_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402894A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT83)
  */
#define CYREG_DW0_CH_STRUCT83_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402894C0UL)
#define CYREG_DW0_CH_STRUCT83_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402894C4UL)
#define CYREG_DW0_CH_STRUCT83_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402894C8UL)
#define CYREG_DW0_CH_STRUCT83_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402894CCUL)
#define CYREG_DW0_CH_STRUCT83_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402894D0UL)
#define CYREG_DW0_CH_STRUCT83_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402894D4UL)
#define CYREG_DW0_CH_STRUCT83_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402894D8UL)
#define CYREG_DW0_CH_STRUCT83_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402894DCUL)
#define CYREG_DW0_CH_STRUCT83_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402894E0UL)
#define CYREG_DW0_CH_STRUCT83_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402894E4UL)
#define CYREG_DW0_CH_STRUCT83_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402894E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT84)
  */
#define CYREG_DW0_CH_STRUCT84_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289500UL)
#define CYREG_DW0_CH_STRUCT84_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289504UL)
#define CYREG_DW0_CH_STRUCT84_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289508UL)
#define CYREG_DW0_CH_STRUCT84_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028950CUL)
#define CYREG_DW0_CH_STRUCT84_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289510UL)
#define CYREG_DW0_CH_STRUCT84_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289514UL)
#define CYREG_DW0_CH_STRUCT84_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289518UL)
#define CYREG_DW0_CH_STRUCT84_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028951CUL)
#define CYREG_DW0_CH_STRUCT84_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40289520UL)
#define CYREG_DW0_CH_STRUCT84_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40289524UL)
#define CYREG_DW0_CH_STRUCT84_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40289528UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT85)
  */
#define CYREG_DW0_CH_STRUCT85_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289540UL)
#define CYREG_DW0_CH_STRUCT85_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289544UL)
#define CYREG_DW0_CH_STRUCT85_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289548UL)
#define CYREG_DW0_CH_STRUCT85_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028954CUL)
#define CYREG_DW0_CH_STRUCT85_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289550UL)
#define CYREG_DW0_CH_STRUCT85_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289554UL)
#define CYREG_DW0_CH_STRUCT85_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289558UL)
#define CYREG_DW0_CH_STRUCT85_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028955CUL)
#define CYREG_DW0_CH_STRUCT85_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40289560UL)
#define CYREG_DW0_CH_STRUCT85_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40289564UL)
#define CYREG_DW0_CH_STRUCT85_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40289568UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT86)
  */
#define CYREG_DW0_CH_STRUCT86_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289580UL)
#define CYREG_DW0_CH_STRUCT86_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289584UL)
#define CYREG_DW0_CH_STRUCT86_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289588UL)
#define CYREG_DW0_CH_STRUCT86_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028958CUL)
#define CYREG_DW0_CH_STRUCT86_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289590UL)
#define CYREG_DW0_CH_STRUCT86_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289594UL)
#define CYREG_DW0_CH_STRUCT86_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289598UL)
#define CYREG_DW0_CH_STRUCT86_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028959CUL)
#define CYREG_DW0_CH_STRUCT86_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402895A0UL)
#define CYREG_DW0_CH_STRUCT86_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402895A4UL)
#define CYREG_DW0_CH_STRUCT86_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402895A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT87)
  */
#define CYREG_DW0_CH_STRUCT87_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402895C0UL)
#define CYREG_DW0_CH_STRUCT87_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402895C4UL)
#define CYREG_DW0_CH_STRUCT87_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402895C8UL)
#define CYREG_DW0_CH_STRUCT87_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402895CCUL)
#define CYREG_DW0_CH_STRUCT87_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402895D0UL)
#define CYREG_DW0_CH_STRUCT87_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402895D4UL)
#define CYREG_DW0_CH_STRUCT87_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402895D8UL)
#define CYREG_DW0_CH_STRUCT87_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402895DCUL)
#define CYREG_DW0_CH_STRUCT87_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402895E0UL)
#define CYREG_DW0_CH_STRUCT87_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402895E4UL)
#define CYREG_DW0_CH_STRUCT87_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402895E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT88)
  */
#define CYREG_DW0_CH_STRUCT88_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289600UL)
#define CYREG_DW0_CH_STRUCT88_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289604UL)
#define CYREG_DW0_CH_STRUCT88_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289608UL)
#define CYREG_DW0_CH_STRUCT88_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028960CUL)
#define CYREG_DW0_CH_STRUCT88_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289610UL)
#define CYREG_DW0_CH_STRUCT88_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289614UL)
#define CYREG_DW0_CH_STRUCT88_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289618UL)
#define CYREG_DW0_CH_STRUCT88_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028961CUL)
#define CYREG_DW0_CH_STRUCT88_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40289620UL)
#define CYREG_DW0_CH_STRUCT88_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40289624UL)
#define CYREG_DW0_CH_STRUCT88_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40289628UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT89)
  */
#define CYREG_DW0_CH_STRUCT89_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289640UL)
#define CYREG_DW0_CH_STRUCT89_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289644UL)
#define CYREG_DW0_CH_STRUCT89_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289648UL)
#define CYREG_DW0_CH_STRUCT89_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028964CUL)
#define CYREG_DW0_CH_STRUCT89_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289650UL)
#define CYREG_DW0_CH_STRUCT89_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289654UL)
#define CYREG_DW0_CH_STRUCT89_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289658UL)
#define CYREG_DW0_CH_STRUCT89_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028965CUL)
#define CYREG_DW0_CH_STRUCT89_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40289660UL)
#define CYREG_DW0_CH_STRUCT89_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40289664UL)
#define CYREG_DW0_CH_STRUCT89_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40289668UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT90)
  */
#define CYREG_DW0_CH_STRUCT90_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289680UL)
#define CYREG_DW0_CH_STRUCT90_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289684UL)
#define CYREG_DW0_CH_STRUCT90_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289688UL)
#define CYREG_DW0_CH_STRUCT90_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028968CUL)
#define CYREG_DW0_CH_STRUCT90_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289690UL)
#define CYREG_DW0_CH_STRUCT90_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289694UL)
#define CYREG_DW0_CH_STRUCT90_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289698UL)
#define CYREG_DW0_CH_STRUCT90_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028969CUL)
#define CYREG_DW0_CH_STRUCT90_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402896A0UL)
#define CYREG_DW0_CH_STRUCT90_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402896A4UL)
#define CYREG_DW0_CH_STRUCT90_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402896A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT91)
  */
#define CYREG_DW0_CH_STRUCT91_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402896C0UL)
#define CYREG_DW0_CH_STRUCT91_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402896C4UL)
#define CYREG_DW0_CH_STRUCT91_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402896C8UL)
#define CYREG_DW0_CH_STRUCT91_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402896CCUL)
#define CYREG_DW0_CH_STRUCT91_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402896D0UL)
#define CYREG_DW0_CH_STRUCT91_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402896D4UL)
#define CYREG_DW0_CH_STRUCT91_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402896D8UL)
#define CYREG_DW0_CH_STRUCT91_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402896DCUL)
#define CYREG_DW0_CH_STRUCT91_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402896E0UL)
#define CYREG_DW0_CH_STRUCT91_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402896E4UL)
#define CYREG_DW0_CH_STRUCT91_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402896E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT92)
  */
#define CYREG_DW0_CH_STRUCT92_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289700UL)
#define CYREG_DW0_CH_STRUCT92_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289704UL)
#define CYREG_DW0_CH_STRUCT92_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289708UL)
#define CYREG_DW0_CH_STRUCT92_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028970CUL)
#define CYREG_DW0_CH_STRUCT92_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289710UL)
#define CYREG_DW0_CH_STRUCT92_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289714UL)
#define CYREG_DW0_CH_STRUCT92_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289718UL)
#define CYREG_DW0_CH_STRUCT92_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028971CUL)
#define CYREG_DW0_CH_STRUCT92_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40289720UL)
#define CYREG_DW0_CH_STRUCT92_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40289724UL)
#define CYREG_DW0_CH_STRUCT92_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40289728UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT93)
  */
#define CYREG_DW0_CH_STRUCT93_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289740UL)
#define CYREG_DW0_CH_STRUCT93_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289744UL)
#define CYREG_DW0_CH_STRUCT93_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289748UL)
#define CYREG_DW0_CH_STRUCT93_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028974CUL)
#define CYREG_DW0_CH_STRUCT93_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289750UL)
#define CYREG_DW0_CH_STRUCT93_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289754UL)
#define CYREG_DW0_CH_STRUCT93_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289758UL)
#define CYREG_DW0_CH_STRUCT93_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028975CUL)
#define CYREG_DW0_CH_STRUCT93_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40289760UL)
#define CYREG_DW0_CH_STRUCT93_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40289764UL)
#define CYREG_DW0_CH_STRUCT93_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40289768UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT94)
  */
#define CYREG_DW0_CH_STRUCT94_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289780UL)
#define CYREG_DW0_CH_STRUCT94_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289784UL)
#define CYREG_DW0_CH_STRUCT94_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289788UL)
#define CYREG_DW0_CH_STRUCT94_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028978CUL)
#define CYREG_DW0_CH_STRUCT94_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289790UL)
#define CYREG_DW0_CH_STRUCT94_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289794UL)
#define CYREG_DW0_CH_STRUCT94_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289798UL)
#define CYREG_DW0_CH_STRUCT94_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028979CUL)
#define CYREG_DW0_CH_STRUCT94_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402897A0UL)
#define CYREG_DW0_CH_STRUCT94_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402897A4UL)
#define CYREG_DW0_CH_STRUCT94_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402897A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT95)
  */
#define CYREG_DW0_CH_STRUCT95_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402897C0UL)
#define CYREG_DW0_CH_STRUCT95_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402897C4UL)
#define CYREG_DW0_CH_STRUCT95_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402897C8UL)
#define CYREG_DW0_CH_STRUCT95_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402897CCUL)
#define CYREG_DW0_CH_STRUCT95_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402897D0UL)
#define CYREG_DW0_CH_STRUCT95_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402897D4UL)
#define CYREG_DW0_CH_STRUCT95_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402897D8UL)
#define CYREG_DW0_CH_STRUCT95_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402897DCUL)
#define CYREG_DW0_CH_STRUCT95_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402897E0UL)
#define CYREG_DW0_CH_STRUCT95_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402897E4UL)
#define CYREG_DW0_CH_STRUCT95_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402897E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT96)
  */
#define CYREG_DW0_CH_STRUCT96_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289800UL)
#define CYREG_DW0_CH_STRUCT96_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289804UL)
#define CYREG_DW0_CH_STRUCT96_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289808UL)
#define CYREG_DW0_CH_STRUCT96_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028980CUL)
#define CYREG_DW0_CH_STRUCT96_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289810UL)
#define CYREG_DW0_CH_STRUCT96_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289814UL)
#define CYREG_DW0_CH_STRUCT96_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289818UL)
#define CYREG_DW0_CH_STRUCT96_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028981CUL)
#define CYREG_DW0_CH_STRUCT96_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40289820UL)
#define CYREG_DW0_CH_STRUCT96_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40289824UL)
#define CYREG_DW0_CH_STRUCT96_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40289828UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT97)
  */
#define CYREG_DW0_CH_STRUCT97_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289840UL)
#define CYREG_DW0_CH_STRUCT97_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289844UL)
#define CYREG_DW0_CH_STRUCT97_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289848UL)
#define CYREG_DW0_CH_STRUCT97_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028984CUL)
#define CYREG_DW0_CH_STRUCT97_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289850UL)
#define CYREG_DW0_CH_STRUCT97_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289854UL)
#define CYREG_DW0_CH_STRUCT97_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289858UL)
#define CYREG_DW0_CH_STRUCT97_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028985CUL)
#define CYREG_DW0_CH_STRUCT97_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40289860UL)
#define CYREG_DW0_CH_STRUCT97_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40289864UL)
#define CYREG_DW0_CH_STRUCT97_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40289868UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT98)
  */
#define CYREG_DW0_CH_STRUCT98_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40289880UL)
#define CYREG_DW0_CH_STRUCT98_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40289884UL)
#define CYREG_DW0_CH_STRUCT98_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40289888UL)
#define CYREG_DW0_CH_STRUCT98_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4028988CUL)
#define CYREG_DW0_CH_STRUCT98_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40289890UL)
#define CYREG_DW0_CH_STRUCT98_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40289894UL)
#define CYREG_DW0_CH_STRUCT98_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40289898UL)
#define CYREG_DW0_CH_STRUCT98_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4028989CUL)
#define CYREG_DW0_CH_STRUCT98_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402898A0UL)
#define CYREG_DW0_CH_STRUCT98_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402898A4UL)
#define CYREG_DW0_CH_STRUCT98_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402898A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT99)
  */
#define CYREG_DW0_CH_STRUCT99_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402898C0UL)
#define CYREG_DW0_CH_STRUCT99_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402898C4UL)
#define CYREG_DW0_CH_STRUCT99_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402898C8UL)
#define CYREG_DW0_CH_STRUCT99_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402898CCUL)
#define CYREG_DW0_CH_STRUCT99_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402898D0UL)
#define CYREG_DW0_CH_STRUCT99_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402898D4UL)
#define CYREG_DW0_CH_STRUCT99_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402898D8UL)
#define CYREG_DW0_CH_STRUCT99_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402898DCUL)
#define CYREG_DW0_CH_STRUCT99_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402898E0UL)
#define CYREG_DW0_CH_STRUCT99_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402898E4UL)
#define CYREG_DW0_CH_STRUCT99_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402898E8UL)

/**
  * \brief Datawire Controller (DW0)
  */
#define CYREG_DW0_CTL0                  ((volatile un_DW_CTL_t*) 0x40280000UL)
#define CYREG_DW0_STATUS0               ((volatile un_DW_STATUS_t*) 0x40280004UL)
#define CYREG_DW0_ACT_DESCR_CTL0        ((volatile un_DW_ACT_DESCR_CTL_t*) 0x40280020UL)
#define CYREG_DW0_ACT_DESCR_SRC0        ((volatile un_DW_ACT_DESCR_SRC_t*) 0x40280024UL)
#define CYREG_DW0_ACT_DESCR_DST0        ((volatile un_DW_ACT_DESCR_DST_t*) 0x40280028UL)
#define CYREG_DW0_ACT_DESCR_X_CTL0      ((volatile un_DW_ACT_DESCR_X_CTL_t*) 0x40280030UL)
#define CYREG_DW0_ACT_DESCR_Y_CTL0      ((volatile un_DW_ACT_DESCR_Y_CTL_t*) 0x40280034UL)
#define CYREG_DW0_ACT_DESCR_NEXT_PTR0   ((volatile un_DW_ACT_DESCR_NEXT_PTR_t*) 0x40280038UL)
#define CYREG_DW0_ACT_SRC0              ((volatile un_DW_ACT_SRC_t*) 0x40280040UL)
#define CYREG_DW0_ACT_DST0              ((volatile un_DW_ACT_DST_t*) 0x40280044UL)
#define CYREG_DW0_ECC_CTL0              ((volatile un_DW_ECC_CTL_t*) 0x40280080UL)
#define CYREG_DW0_CRC_CTL0              ((volatile un_DW_CRC_CTL_t*) 0x40280100UL)
#define CYREG_DW0_CRC_DATA_CTL0         ((volatile un_DW_CRC_DATA_CTL_t*) 0x40280110UL)
#define CYREG_DW0_CRC_POL_CTL0          ((volatile un_DW_CRC_POL_CTL_t*) 0x40280120UL)
#define CYREG_DW0_CRC_LFSR_CTL0         ((volatile un_DW_CRC_LFSR_CTL_t*) 0x40280130UL)
#define CYREG_DW0_CRC_REM_CTL0          ((volatile un_DW_CRC_REM_CTL_t*) 0x40280140UL)
#define CYREG_DW0_CRC_REM_RESULT0       ((volatile un_DW_CRC_REM_RESULT_t*) 0x40280148UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT0)
  */
#define CYREG_DW1_CH_STRUCT0_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298000UL)
#define CYREG_DW1_CH_STRUCT0_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298004UL)
#define CYREG_DW1_CH_STRUCT0_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298008UL)
#define CYREG_DW1_CH_STRUCT0_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029800CUL)
#define CYREG_DW1_CH_STRUCT0_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298010UL)
#define CYREG_DW1_CH_STRUCT0_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298014UL)
#define CYREG_DW1_CH_STRUCT0_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298018UL)
#define CYREG_DW1_CH_STRUCT0_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029801CUL)
#define CYREG_DW1_CH_STRUCT0_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298020UL)
#define CYREG_DW1_CH_STRUCT0_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298024UL)
#define CYREG_DW1_CH_STRUCT0_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298028UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT1)
  */
#define CYREG_DW1_CH_STRUCT1_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298040UL)
#define CYREG_DW1_CH_STRUCT1_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298044UL)
#define CYREG_DW1_CH_STRUCT1_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298048UL)
#define CYREG_DW1_CH_STRUCT1_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029804CUL)
#define CYREG_DW1_CH_STRUCT1_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298050UL)
#define CYREG_DW1_CH_STRUCT1_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298054UL)
#define CYREG_DW1_CH_STRUCT1_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298058UL)
#define CYREG_DW1_CH_STRUCT1_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029805CUL)
#define CYREG_DW1_CH_STRUCT1_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298060UL)
#define CYREG_DW1_CH_STRUCT1_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298064UL)
#define CYREG_DW1_CH_STRUCT1_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298068UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT2)
  */
#define CYREG_DW1_CH_STRUCT2_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298080UL)
#define CYREG_DW1_CH_STRUCT2_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298084UL)
#define CYREG_DW1_CH_STRUCT2_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298088UL)
#define CYREG_DW1_CH_STRUCT2_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029808CUL)
#define CYREG_DW1_CH_STRUCT2_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298090UL)
#define CYREG_DW1_CH_STRUCT2_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298094UL)
#define CYREG_DW1_CH_STRUCT2_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298098UL)
#define CYREG_DW1_CH_STRUCT2_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029809CUL)
#define CYREG_DW1_CH_STRUCT2_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402980A0UL)
#define CYREG_DW1_CH_STRUCT2_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402980A4UL)
#define CYREG_DW1_CH_STRUCT2_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402980A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT3)
  */
#define CYREG_DW1_CH_STRUCT3_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402980C0UL)
#define CYREG_DW1_CH_STRUCT3_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402980C4UL)
#define CYREG_DW1_CH_STRUCT3_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402980C8UL)
#define CYREG_DW1_CH_STRUCT3_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402980CCUL)
#define CYREG_DW1_CH_STRUCT3_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402980D0UL)
#define CYREG_DW1_CH_STRUCT3_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402980D4UL)
#define CYREG_DW1_CH_STRUCT3_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402980D8UL)
#define CYREG_DW1_CH_STRUCT3_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402980DCUL)
#define CYREG_DW1_CH_STRUCT3_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402980E0UL)
#define CYREG_DW1_CH_STRUCT3_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402980E4UL)
#define CYREG_DW1_CH_STRUCT3_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402980E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT4)
  */
#define CYREG_DW1_CH_STRUCT4_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298100UL)
#define CYREG_DW1_CH_STRUCT4_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298104UL)
#define CYREG_DW1_CH_STRUCT4_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298108UL)
#define CYREG_DW1_CH_STRUCT4_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029810CUL)
#define CYREG_DW1_CH_STRUCT4_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298110UL)
#define CYREG_DW1_CH_STRUCT4_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298114UL)
#define CYREG_DW1_CH_STRUCT4_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298118UL)
#define CYREG_DW1_CH_STRUCT4_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029811CUL)
#define CYREG_DW1_CH_STRUCT4_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298120UL)
#define CYREG_DW1_CH_STRUCT4_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298124UL)
#define CYREG_DW1_CH_STRUCT4_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298128UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT5)
  */
#define CYREG_DW1_CH_STRUCT5_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298140UL)
#define CYREG_DW1_CH_STRUCT5_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298144UL)
#define CYREG_DW1_CH_STRUCT5_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298148UL)
#define CYREG_DW1_CH_STRUCT5_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029814CUL)
#define CYREG_DW1_CH_STRUCT5_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298150UL)
#define CYREG_DW1_CH_STRUCT5_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298154UL)
#define CYREG_DW1_CH_STRUCT5_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298158UL)
#define CYREG_DW1_CH_STRUCT5_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029815CUL)
#define CYREG_DW1_CH_STRUCT5_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298160UL)
#define CYREG_DW1_CH_STRUCT5_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298164UL)
#define CYREG_DW1_CH_STRUCT5_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298168UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT6)
  */
#define CYREG_DW1_CH_STRUCT6_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298180UL)
#define CYREG_DW1_CH_STRUCT6_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298184UL)
#define CYREG_DW1_CH_STRUCT6_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298188UL)
#define CYREG_DW1_CH_STRUCT6_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029818CUL)
#define CYREG_DW1_CH_STRUCT6_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298190UL)
#define CYREG_DW1_CH_STRUCT6_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298194UL)
#define CYREG_DW1_CH_STRUCT6_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298198UL)
#define CYREG_DW1_CH_STRUCT6_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029819CUL)
#define CYREG_DW1_CH_STRUCT6_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402981A0UL)
#define CYREG_DW1_CH_STRUCT6_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402981A4UL)
#define CYREG_DW1_CH_STRUCT6_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402981A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT7)
  */
#define CYREG_DW1_CH_STRUCT7_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402981C0UL)
#define CYREG_DW1_CH_STRUCT7_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402981C4UL)
#define CYREG_DW1_CH_STRUCT7_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402981C8UL)
#define CYREG_DW1_CH_STRUCT7_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402981CCUL)
#define CYREG_DW1_CH_STRUCT7_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402981D0UL)
#define CYREG_DW1_CH_STRUCT7_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402981D4UL)
#define CYREG_DW1_CH_STRUCT7_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402981D8UL)
#define CYREG_DW1_CH_STRUCT7_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402981DCUL)
#define CYREG_DW1_CH_STRUCT7_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402981E0UL)
#define CYREG_DW1_CH_STRUCT7_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402981E4UL)
#define CYREG_DW1_CH_STRUCT7_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402981E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT8)
  */
#define CYREG_DW1_CH_STRUCT8_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298200UL)
#define CYREG_DW1_CH_STRUCT8_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298204UL)
#define CYREG_DW1_CH_STRUCT8_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298208UL)
#define CYREG_DW1_CH_STRUCT8_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029820CUL)
#define CYREG_DW1_CH_STRUCT8_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298210UL)
#define CYREG_DW1_CH_STRUCT8_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298214UL)
#define CYREG_DW1_CH_STRUCT8_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298218UL)
#define CYREG_DW1_CH_STRUCT8_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029821CUL)
#define CYREG_DW1_CH_STRUCT8_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298220UL)
#define CYREG_DW1_CH_STRUCT8_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298224UL)
#define CYREG_DW1_CH_STRUCT8_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298228UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT9)
  */
#define CYREG_DW1_CH_STRUCT9_CH_CTL     ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298240UL)
#define CYREG_DW1_CH_STRUCT9_CH_STATUS  ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298244UL)
#define CYREG_DW1_CH_STRUCT9_CH_IDX     ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298248UL)
#define CYREG_DW1_CH_STRUCT9_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029824CUL)
#define CYREG_DW1_CH_STRUCT9_INTR       ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298250UL)
#define CYREG_DW1_CH_STRUCT9_INTR_SET   ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298254UL)
#define CYREG_DW1_CH_STRUCT9_INTR_MASK  ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298258UL)
#define CYREG_DW1_CH_STRUCT9_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029825CUL)
#define CYREG_DW1_CH_STRUCT9_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298260UL)
#define CYREG_DW1_CH_STRUCT9_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298264UL)
#define CYREG_DW1_CH_STRUCT9_TR_CMD     ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298268UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT10)
  */
#define CYREG_DW1_CH_STRUCT10_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298280UL)
#define CYREG_DW1_CH_STRUCT10_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298284UL)
#define CYREG_DW1_CH_STRUCT10_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298288UL)
#define CYREG_DW1_CH_STRUCT10_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029828CUL)
#define CYREG_DW1_CH_STRUCT10_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298290UL)
#define CYREG_DW1_CH_STRUCT10_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298294UL)
#define CYREG_DW1_CH_STRUCT10_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298298UL)
#define CYREG_DW1_CH_STRUCT10_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029829CUL)
#define CYREG_DW1_CH_STRUCT10_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402982A0UL)
#define CYREG_DW1_CH_STRUCT10_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402982A4UL)
#define CYREG_DW1_CH_STRUCT10_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402982A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT11)
  */
#define CYREG_DW1_CH_STRUCT11_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402982C0UL)
#define CYREG_DW1_CH_STRUCT11_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402982C4UL)
#define CYREG_DW1_CH_STRUCT11_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402982C8UL)
#define CYREG_DW1_CH_STRUCT11_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402982CCUL)
#define CYREG_DW1_CH_STRUCT11_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402982D0UL)
#define CYREG_DW1_CH_STRUCT11_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402982D4UL)
#define CYREG_DW1_CH_STRUCT11_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402982D8UL)
#define CYREG_DW1_CH_STRUCT11_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402982DCUL)
#define CYREG_DW1_CH_STRUCT11_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402982E0UL)
#define CYREG_DW1_CH_STRUCT11_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402982E4UL)
#define CYREG_DW1_CH_STRUCT11_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402982E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT12)
  */
#define CYREG_DW1_CH_STRUCT12_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298300UL)
#define CYREG_DW1_CH_STRUCT12_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298304UL)
#define CYREG_DW1_CH_STRUCT12_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298308UL)
#define CYREG_DW1_CH_STRUCT12_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029830CUL)
#define CYREG_DW1_CH_STRUCT12_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298310UL)
#define CYREG_DW1_CH_STRUCT12_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298314UL)
#define CYREG_DW1_CH_STRUCT12_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298318UL)
#define CYREG_DW1_CH_STRUCT12_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029831CUL)
#define CYREG_DW1_CH_STRUCT12_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298320UL)
#define CYREG_DW1_CH_STRUCT12_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298324UL)
#define CYREG_DW1_CH_STRUCT12_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298328UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT13)
  */
#define CYREG_DW1_CH_STRUCT13_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298340UL)
#define CYREG_DW1_CH_STRUCT13_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298344UL)
#define CYREG_DW1_CH_STRUCT13_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298348UL)
#define CYREG_DW1_CH_STRUCT13_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029834CUL)
#define CYREG_DW1_CH_STRUCT13_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298350UL)
#define CYREG_DW1_CH_STRUCT13_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298354UL)
#define CYREG_DW1_CH_STRUCT13_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298358UL)
#define CYREG_DW1_CH_STRUCT13_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029835CUL)
#define CYREG_DW1_CH_STRUCT13_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298360UL)
#define CYREG_DW1_CH_STRUCT13_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298364UL)
#define CYREG_DW1_CH_STRUCT13_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298368UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT14)
  */
#define CYREG_DW1_CH_STRUCT14_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298380UL)
#define CYREG_DW1_CH_STRUCT14_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298384UL)
#define CYREG_DW1_CH_STRUCT14_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298388UL)
#define CYREG_DW1_CH_STRUCT14_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029838CUL)
#define CYREG_DW1_CH_STRUCT14_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298390UL)
#define CYREG_DW1_CH_STRUCT14_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298394UL)
#define CYREG_DW1_CH_STRUCT14_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298398UL)
#define CYREG_DW1_CH_STRUCT14_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029839CUL)
#define CYREG_DW1_CH_STRUCT14_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402983A0UL)
#define CYREG_DW1_CH_STRUCT14_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402983A4UL)
#define CYREG_DW1_CH_STRUCT14_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402983A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT15)
  */
#define CYREG_DW1_CH_STRUCT15_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402983C0UL)
#define CYREG_DW1_CH_STRUCT15_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402983C4UL)
#define CYREG_DW1_CH_STRUCT15_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402983C8UL)
#define CYREG_DW1_CH_STRUCT15_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402983CCUL)
#define CYREG_DW1_CH_STRUCT15_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402983D0UL)
#define CYREG_DW1_CH_STRUCT15_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402983D4UL)
#define CYREG_DW1_CH_STRUCT15_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402983D8UL)
#define CYREG_DW1_CH_STRUCT15_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402983DCUL)
#define CYREG_DW1_CH_STRUCT15_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402983E0UL)
#define CYREG_DW1_CH_STRUCT15_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402983E4UL)
#define CYREG_DW1_CH_STRUCT15_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402983E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT16)
  */
#define CYREG_DW1_CH_STRUCT16_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298400UL)
#define CYREG_DW1_CH_STRUCT16_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298404UL)
#define CYREG_DW1_CH_STRUCT16_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298408UL)
#define CYREG_DW1_CH_STRUCT16_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029840CUL)
#define CYREG_DW1_CH_STRUCT16_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298410UL)
#define CYREG_DW1_CH_STRUCT16_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298414UL)
#define CYREG_DW1_CH_STRUCT16_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298418UL)
#define CYREG_DW1_CH_STRUCT16_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029841CUL)
#define CYREG_DW1_CH_STRUCT16_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298420UL)
#define CYREG_DW1_CH_STRUCT16_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298424UL)
#define CYREG_DW1_CH_STRUCT16_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298428UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT17)
  */
#define CYREG_DW1_CH_STRUCT17_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298440UL)
#define CYREG_DW1_CH_STRUCT17_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298444UL)
#define CYREG_DW1_CH_STRUCT17_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298448UL)
#define CYREG_DW1_CH_STRUCT17_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029844CUL)
#define CYREG_DW1_CH_STRUCT17_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298450UL)
#define CYREG_DW1_CH_STRUCT17_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298454UL)
#define CYREG_DW1_CH_STRUCT17_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298458UL)
#define CYREG_DW1_CH_STRUCT17_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029845CUL)
#define CYREG_DW1_CH_STRUCT17_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298460UL)
#define CYREG_DW1_CH_STRUCT17_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298464UL)
#define CYREG_DW1_CH_STRUCT17_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298468UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT18)
  */
#define CYREG_DW1_CH_STRUCT18_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298480UL)
#define CYREG_DW1_CH_STRUCT18_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298484UL)
#define CYREG_DW1_CH_STRUCT18_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298488UL)
#define CYREG_DW1_CH_STRUCT18_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029848CUL)
#define CYREG_DW1_CH_STRUCT18_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298490UL)
#define CYREG_DW1_CH_STRUCT18_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298494UL)
#define CYREG_DW1_CH_STRUCT18_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298498UL)
#define CYREG_DW1_CH_STRUCT18_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029849CUL)
#define CYREG_DW1_CH_STRUCT18_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402984A0UL)
#define CYREG_DW1_CH_STRUCT18_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402984A4UL)
#define CYREG_DW1_CH_STRUCT18_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402984A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT19)
  */
#define CYREG_DW1_CH_STRUCT19_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402984C0UL)
#define CYREG_DW1_CH_STRUCT19_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402984C4UL)
#define CYREG_DW1_CH_STRUCT19_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402984C8UL)
#define CYREG_DW1_CH_STRUCT19_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402984CCUL)
#define CYREG_DW1_CH_STRUCT19_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402984D0UL)
#define CYREG_DW1_CH_STRUCT19_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402984D4UL)
#define CYREG_DW1_CH_STRUCT19_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402984D8UL)
#define CYREG_DW1_CH_STRUCT19_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402984DCUL)
#define CYREG_DW1_CH_STRUCT19_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402984E0UL)
#define CYREG_DW1_CH_STRUCT19_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402984E4UL)
#define CYREG_DW1_CH_STRUCT19_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402984E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT20)
  */
#define CYREG_DW1_CH_STRUCT20_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298500UL)
#define CYREG_DW1_CH_STRUCT20_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298504UL)
#define CYREG_DW1_CH_STRUCT20_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298508UL)
#define CYREG_DW1_CH_STRUCT20_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029850CUL)
#define CYREG_DW1_CH_STRUCT20_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298510UL)
#define CYREG_DW1_CH_STRUCT20_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298514UL)
#define CYREG_DW1_CH_STRUCT20_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298518UL)
#define CYREG_DW1_CH_STRUCT20_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029851CUL)
#define CYREG_DW1_CH_STRUCT20_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298520UL)
#define CYREG_DW1_CH_STRUCT20_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298524UL)
#define CYREG_DW1_CH_STRUCT20_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298528UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT21)
  */
#define CYREG_DW1_CH_STRUCT21_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298540UL)
#define CYREG_DW1_CH_STRUCT21_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298544UL)
#define CYREG_DW1_CH_STRUCT21_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298548UL)
#define CYREG_DW1_CH_STRUCT21_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029854CUL)
#define CYREG_DW1_CH_STRUCT21_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298550UL)
#define CYREG_DW1_CH_STRUCT21_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298554UL)
#define CYREG_DW1_CH_STRUCT21_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298558UL)
#define CYREG_DW1_CH_STRUCT21_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029855CUL)
#define CYREG_DW1_CH_STRUCT21_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298560UL)
#define CYREG_DW1_CH_STRUCT21_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298564UL)
#define CYREG_DW1_CH_STRUCT21_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298568UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT22)
  */
#define CYREG_DW1_CH_STRUCT22_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298580UL)
#define CYREG_DW1_CH_STRUCT22_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298584UL)
#define CYREG_DW1_CH_STRUCT22_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298588UL)
#define CYREG_DW1_CH_STRUCT22_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029858CUL)
#define CYREG_DW1_CH_STRUCT22_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298590UL)
#define CYREG_DW1_CH_STRUCT22_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298594UL)
#define CYREG_DW1_CH_STRUCT22_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298598UL)
#define CYREG_DW1_CH_STRUCT22_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029859CUL)
#define CYREG_DW1_CH_STRUCT22_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402985A0UL)
#define CYREG_DW1_CH_STRUCT22_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402985A4UL)
#define CYREG_DW1_CH_STRUCT22_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402985A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT23)
  */
#define CYREG_DW1_CH_STRUCT23_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402985C0UL)
#define CYREG_DW1_CH_STRUCT23_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402985C4UL)
#define CYREG_DW1_CH_STRUCT23_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402985C8UL)
#define CYREG_DW1_CH_STRUCT23_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402985CCUL)
#define CYREG_DW1_CH_STRUCT23_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402985D0UL)
#define CYREG_DW1_CH_STRUCT23_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402985D4UL)
#define CYREG_DW1_CH_STRUCT23_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402985D8UL)
#define CYREG_DW1_CH_STRUCT23_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402985DCUL)
#define CYREG_DW1_CH_STRUCT23_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402985E0UL)
#define CYREG_DW1_CH_STRUCT23_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402985E4UL)
#define CYREG_DW1_CH_STRUCT23_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402985E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT24)
  */
#define CYREG_DW1_CH_STRUCT24_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298600UL)
#define CYREG_DW1_CH_STRUCT24_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298604UL)
#define CYREG_DW1_CH_STRUCT24_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298608UL)
#define CYREG_DW1_CH_STRUCT24_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029860CUL)
#define CYREG_DW1_CH_STRUCT24_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298610UL)
#define CYREG_DW1_CH_STRUCT24_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298614UL)
#define CYREG_DW1_CH_STRUCT24_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298618UL)
#define CYREG_DW1_CH_STRUCT24_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029861CUL)
#define CYREG_DW1_CH_STRUCT24_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298620UL)
#define CYREG_DW1_CH_STRUCT24_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298624UL)
#define CYREG_DW1_CH_STRUCT24_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298628UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT25)
  */
#define CYREG_DW1_CH_STRUCT25_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298640UL)
#define CYREG_DW1_CH_STRUCT25_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298644UL)
#define CYREG_DW1_CH_STRUCT25_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298648UL)
#define CYREG_DW1_CH_STRUCT25_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029864CUL)
#define CYREG_DW1_CH_STRUCT25_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298650UL)
#define CYREG_DW1_CH_STRUCT25_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298654UL)
#define CYREG_DW1_CH_STRUCT25_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298658UL)
#define CYREG_DW1_CH_STRUCT25_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029865CUL)
#define CYREG_DW1_CH_STRUCT25_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298660UL)
#define CYREG_DW1_CH_STRUCT25_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298664UL)
#define CYREG_DW1_CH_STRUCT25_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298668UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT26)
  */
#define CYREG_DW1_CH_STRUCT26_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298680UL)
#define CYREG_DW1_CH_STRUCT26_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298684UL)
#define CYREG_DW1_CH_STRUCT26_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298688UL)
#define CYREG_DW1_CH_STRUCT26_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029868CUL)
#define CYREG_DW1_CH_STRUCT26_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298690UL)
#define CYREG_DW1_CH_STRUCT26_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298694UL)
#define CYREG_DW1_CH_STRUCT26_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298698UL)
#define CYREG_DW1_CH_STRUCT26_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029869CUL)
#define CYREG_DW1_CH_STRUCT26_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402986A0UL)
#define CYREG_DW1_CH_STRUCT26_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402986A4UL)
#define CYREG_DW1_CH_STRUCT26_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402986A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT27)
  */
#define CYREG_DW1_CH_STRUCT27_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402986C0UL)
#define CYREG_DW1_CH_STRUCT27_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402986C4UL)
#define CYREG_DW1_CH_STRUCT27_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402986C8UL)
#define CYREG_DW1_CH_STRUCT27_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402986CCUL)
#define CYREG_DW1_CH_STRUCT27_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402986D0UL)
#define CYREG_DW1_CH_STRUCT27_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402986D4UL)
#define CYREG_DW1_CH_STRUCT27_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402986D8UL)
#define CYREG_DW1_CH_STRUCT27_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402986DCUL)
#define CYREG_DW1_CH_STRUCT27_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402986E0UL)
#define CYREG_DW1_CH_STRUCT27_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402986E4UL)
#define CYREG_DW1_CH_STRUCT27_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402986E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT28)
  */
#define CYREG_DW1_CH_STRUCT28_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298700UL)
#define CYREG_DW1_CH_STRUCT28_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298704UL)
#define CYREG_DW1_CH_STRUCT28_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298708UL)
#define CYREG_DW1_CH_STRUCT28_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029870CUL)
#define CYREG_DW1_CH_STRUCT28_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298710UL)
#define CYREG_DW1_CH_STRUCT28_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298714UL)
#define CYREG_DW1_CH_STRUCT28_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298718UL)
#define CYREG_DW1_CH_STRUCT28_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029871CUL)
#define CYREG_DW1_CH_STRUCT28_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298720UL)
#define CYREG_DW1_CH_STRUCT28_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298724UL)
#define CYREG_DW1_CH_STRUCT28_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298728UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT29)
  */
#define CYREG_DW1_CH_STRUCT29_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298740UL)
#define CYREG_DW1_CH_STRUCT29_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298744UL)
#define CYREG_DW1_CH_STRUCT29_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298748UL)
#define CYREG_DW1_CH_STRUCT29_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029874CUL)
#define CYREG_DW1_CH_STRUCT29_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298750UL)
#define CYREG_DW1_CH_STRUCT29_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298754UL)
#define CYREG_DW1_CH_STRUCT29_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298758UL)
#define CYREG_DW1_CH_STRUCT29_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029875CUL)
#define CYREG_DW1_CH_STRUCT29_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298760UL)
#define CYREG_DW1_CH_STRUCT29_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298764UL)
#define CYREG_DW1_CH_STRUCT29_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298768UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT30)
  */
#define CYREG_DW1_CH_STRUCT30_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298780UL)
#define CYREG_DW1_CH_STRUCT30_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298784UL)
#define CYREG_DW1_CH_STRUCT30_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298788UL)
#define CYREG_DW1_CH_STRUCT30_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029878CUL)
#define CYREG_DW1_CH_STRUCT30_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298790UL)
#define CYREG_DW1_CH_STRUCT30_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298794UL)
#define CYREG_DW1_CH_STRUCT30_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298798UL)
#define CYREG_DW1_CH_STRUCT30_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029879CUL)
#define CYREG_DW1_CH_STRUCT30_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402987A0UL)
#define CYREG_DW1_CH_STRUCT30_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402987A4UL)
#define CYREG_DW1_CH_STRUCT30_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402987A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT31)
  */
#define CYREG_DW1_CH_STRUCT31_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402987C0UL)
#define CYREG_DW1_CH_STRUCT31_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402987C4UL)
#define CYREG_DW1_CH_STRUCT31_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402987C8UL)
#define CYREG_DW1_CH_STRUCT31_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402987CCUL)
#define CYREG_DW1_CH_STRUCT31_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402987D0UL)
#define CYREG_DW1_CH_STRUCT31_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402987D4UL)
#define CYREG_DW1_CH_STRUCT31_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402987D8UL)
#define CYREG_DW1_CH_STRUCT31_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402987DCUL)
#define CYREG_DW1_CH_STRUCT31_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402987E0UL)
#define CYREG_DW1_CH_STRUCT31_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402987E4UL)
#define CYREG_DW1_CH_STRUCT31_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402987E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT32)
  */
#define CYREG_DW1_CH_STRUCT32_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298800UL)
#define CYREG_DW1_CH_STRUCT32_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298804UL)
#define CYREG_DW1_CH_STRUCT32_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298808UL)
#define CYREG_DW1_CH_STRUCT32_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029880CUL)
#define CYREG_DW1_CH_STRUCT32_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298810UL)
#define CYREG_DW1_CH_STRUCT32_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298814UL)
#define CYREG_DW1_CH_STRUCT32_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298818UL)
#define CYREG_DW1_CH_STRUCT32_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029881CUL)
#define CYREG_DW1_CH_STRUCT32_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298820UL)
#define CYREG_DW1_CH_STRUCT32_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298824UL)
#define CYREG_DW1_CH_STRUCT32_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298828UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT33)
  */
#define CYREG_DW1_CH_STRUCT33_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298840UL)
#define CYREG_DW1_CH_STRUCT33_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298844UL)
#define CYREG_DW1_CH_STRUCT33_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298848UL)
#define CYREG_DW1_CH_STRUCT33_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029884CUL)
#define CYREG_DW1_CH_STRUCT33_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298850UL)
#define CYREG_DW1_CH_STRUCT33_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298854UL)
#define CYREG_DW1_CH_STRUCT33_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298858UL)
#define CYREG_DW1_CH_STRUCT33_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029885CUL)
#define CYREG_DW1_CH_STRUCT33_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298860UL)
#define CYREG_DW1_CH_STRUCT33_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298864UL)
#define CYREG_DW1_CH_STRUCT33_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298868UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT34)
  */
#define CYREG_DW1_CH_STRUCT34_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298880UL)
#define CYREG_DW1_CH_STRUCT34_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298884UL)
#define CYREG_DW1_CH_STRUCT34_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298888UL)
#define CYREG_DW1_CH_STRUCT34_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029888CUL)
#define CYREG_DW1_CH_STRUCT34_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298890UL)
#define CYREG_DW1_CH_STRUCT34_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298894UL)
#define CYREG_DW1_CH_STRUCT34_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298898UL)
#define CYREG_DW1_CH_STRUCT34_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029889CUL)
#define CYREG_DW1_CH_STRUCT34_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402988A0UL)
#define CYREG_DW1_CH_STRUCT34_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402988A4UL)
#define CYREG_DW1_CH_STRUCT34_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402988A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT35)
  */
#define CYREG_DW1_CH_STRUCT35_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402988C0UL)
#define CYREG_DW1_CH_STRUCT35_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402988C4UL)
#define CYREG_DW1_CH_STRUCT35_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402988C8UL)
#define CYREG_DW1_CH_STRUCT35_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402988CCUL)
#define CYREG_DW1_CH_STRUCT35_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402988D0UL)
#define CYREG_DW1_CH_STRUCT35_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402988D4UL)
#define CYREG_DW1_CH_STRUCT35_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402988D8UL)
#define CYREG_DW1_CH_STRUCT35_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402988DCUL)
#define CYREG_DW1_CH_STRUCT35_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402988E0UL)
#define CYREG_DW1_CH_STRUCT35_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402988E4UL)
#define CYREG_DW1_CH_STRUCT35_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402988E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT36)
  */
#define CYREG_DW1_CH_STRUCT36_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298900UL)
#define CYREG_DW1_CH_STRUCT36_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298904UL)
#define CYREG_DW1_CH_STRUCT36_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298908UL)
#define CYREG_DW1_CH_STRUCT36_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029890CUL)
#define CYREG_DW1_CH_STRUCT36_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298910UL)
#define CYREG_DW1_CH_STRUCT36_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298914UL)
#define CYREG_DW1_CH_STRUCT36_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298918UL)
#define CYREG_DW1_CH_STRUCT36_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029891CUL)
#define CYREG_DW1_CH_STRUCT36_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298920UL)
#define CYREG_DW1_CH_STRUCT36_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298924UL)
#define CYREG_DW1_CH_STRUCT36_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298928UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT37)
  */
#define CYREG_DW1_CH_STRUCT37_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298940UL)
#define CYREG_DW1_CH_STRUCT37_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298944UL)
#define CYREG_DW1_CH_STRUCT37_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298948UL)
#define CYREG_DW1_CH_STRUCT37_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029894CUL)
#define CYREG_DW1_CH_STRUCT37_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298950UL)
#define CYREG_DW1_CH_STRUCT37_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298954UL)
#define CYREG_DW1_CH_STRUCT37_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298958UL)
#define CYREG_DW1_CH_STRUCT37_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029895CUL)
#define CYREG_DW1_CH_STRUCT37_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298960UL)
#define CYREG_DW1_CH_STRUCT37_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298964UL)
#define CYREG_DW1_CH_STRUCT37_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298968UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT38)
  */
#define CYREG_DW1_CH_STRUCT38_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298980UL)
#define CYREG_DW1_CH_STRUCT38_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298984UL)
#define CYREG_DW1_CH_STRUCT38_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298988UL)
#define CYREG_DW1_CH_STRUCT38_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x4029898CUL)
#define CYREG_DW1_CH_STRUCT38_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298990UL)
#define CYREG_DW1_CH_STRUCT38_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298994UL)
#define CYREG_DW1_CH_STRUCT38_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298998UL)
#define CYREG_DW1_CH_STRUCT38_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x4029899CUL)
#define CYREG_DW1_CH_STRUCT38_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402989A0UL)
#define CYREG_DW1_CH_STRUCT38_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402989A4UL)
#define CYREG_DW1_CH_STRUCT38_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402989A8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT39)
  */
#define CYREG_DW1_CH_STRUCT39_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x402989C0UL)
#define CYREG_DW1_CH_STRUCT39_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x402989C4UL)
#define CYREG_DW1_CH_STRUCT39_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x402989C8UL)
#define CYREG_DW1_CH_STRUCT39_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x402989CCUL)
#define CYREG_DW1_CH_STRUCT39_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x402989D0UL)
#define CYREG_DW1_CH_STRUCT39_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x402989D4UL)
#define CYREG_DW1_CH_STRUCT39_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x402989D8UL)
#define CYREG_DW1_CH_STRUCT39_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x402989DCUL)
#define CYREG_DW1_CH_STRUCT39_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x402989E0UL)
#define CYREG_DW1_CH_STRUCT39_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x402989E4UL)
#define CYREG_DW1_CH_STRUCT39_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x402989E8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT40)
  */
#define CYREG_DW1_CH_STRUCT40_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298A00UL)
#define CYREG_DW1_CH_STRUCT40_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298A04UL)
#define CYREG_DW1_CH_STRUCT40_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298A08UL)
#define CYREG_DW1_CH_STRUCT40_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40298A0CUL)
#define CYREG_DW1_CH_STRUCT40_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298A10UL)
#define CYREG_DW1_CH_STRUCT40_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298A14UL)
#define CYREG_DW1_CH_STRUCT40_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298A18UL)
#define CYREG_DW1_CH_STRUCT40_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40298A1CUL)
#define CYREG_DW1_CH_STRUCT40_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298A20UL)
#define CYREG_DW1_CH_STRUCT40_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298A24UL)
#define CYREG_DW1_CH_STRUCT40_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298A28UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT41)
  */
#define CYREG_DW1_CH_STRUCT41_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298A40UL)
#define CYREG_DW1_CH_STRUCT41_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298A44UL)
#define CYREG_DW1_CH_STRUCT41_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298A48UL)
#define CYREG_DW1_CH_STRUCT41_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40298A4CUL)
#define CYREG_DW1_CH_STRUCT41_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298A50UL)
#define CYREG_DW1_CH_STRUCT41_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298A54UL)
#define CYREG_DW1_CH_STRUCT41_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298A58UL)
#define CYREG_DW1_CH_STRUCT41_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40298A5CUL)
#define CYREG_DW1_CH_STRUCT41_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298A60UL)
#define CYREG_DW1_CH_STRUCT41_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298A64UL)
#define CYREG_DW1_CH_STRUCT41_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298A68UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT42)
  */
#define CYREG_DW1_CH_STRUCT42_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298A80UL)
#define CYREG_DW1_CH_STRUCT42_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298A84UL)
#define CYREG_DW1_CH_STRUCT42_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298A88UL)
#define CYREG_DW1_CH_STRUCT42_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40298A8CUL)
#define CYREG_DW1_CH_STRUCT42_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298A90UL)
#define CYREG_DW1_CH_STRUCT42_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298A94UL)
#define CYREG_DW1_CH_STRUCT42_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298A98UL)
#define CYREG_DW1_CH_STRUCT42_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40298A9CUL)
#define CYREG_DW1_CH_STRUCT42_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298AA0UL)
#define CYREG_DW1_CH_STRUCT42_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298AA4UL)
#define CYREG_DW1_CH_STRUCT42_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298AA8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT43)
  */
#define CYREG_DW1_CH_STRUCT43_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298AC0UL)
#define CYREG_DW1_CH_STRUCT43_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298AC4UL)
#define CYREG_DW1_CH_STRUCT43_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298AC8UL)
#define CYREG_DW1_CH_STRUCT43_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40298ACCUL)
#define CYREG_DW1_CH_STRUCT43_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298AD0UL)
#define CYREG_DW1_CH_STRUCT43_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298AD4UL)
#define CYREG_DW1_CH_STRUCT43_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298AD8UL)
#define CYREG_DW1_CH_STRUCT43_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40298ADCUL)
#define CYREG_DW1_CH_STRUCT43_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298AE0UL)
#define CYREG_DW1_CH_STRUCT43_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298AE4UL)
#define CYREG_DW1_CH_STRUCT43_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298AE8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT44)
  */
#define CYREG_DW1_CH_STRUCT44_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298B00UL)
#define CYREG_DW1_CH_STRUCT44_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298B04UL)
#define CYREG_DW1_CH_STRUCT44_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298B08UL)
#define CYREG_DW1_CH_STRUCT44_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40298B0CUL)
#define CYREG_DW1_CH_STRUCT44_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298B10UL)
#define CYREG_DW1_CH_STRUCT44_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298B14UL)
#define CYREG_DW1_CH_STRUCT44_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298B18UL)
#define CYREG_DW1_CH_STRUCT44_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40298B1CUL)
#define CYREG_DW1_CH_STRUCT44_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298B20UL)
#define CYREG_DW1_CH_STRUCT44_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298B24UL)
#define CYREG_DW1_CH_STRUCT44_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298B28UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT45)
  */
#define CYREG_DW1_CH_STRUCT45_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298B40UL)
#define CYREG_DW1_CH_STRUCT45_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298B44UL)
#define CYREG_DW1_CH_STRUCT45_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298B48UL)
#define CYREG_DW1_CH_STRUCT45_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40298B4CUL)
#define CYREG_DW1_CH_STRUCT45_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298B50UL)
#define CYREG_DW1_CH_STRUCT45_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298B54UL)
#define CYREG_DW1_CH_STRUCT45_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298B58UL)
#define CYREG_DW1_CH_STRUCT45_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40298B5CUL)
#define CYREG_DW1_CH_STRUCT45_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298B60UL)
#define CYREG_DW1_CH_STRUCT45_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298B64UL)
#define CYREG_DW1_CH_STRUCT45_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298B68UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT46)
  */
#define CYREG_DW1_CH_STRUCT46_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298B80UL)
#define CYREG_DW1_CH_STRUCT46_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298B84UL)
#define CYREG_DW1_CH_STRUCT46_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298B88UL)
#define CYREG_DW1_CH_STRUCT46_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40298B8CUL)
#define CYREG_DW1_CH_STRUCT46_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298B90UL)
#define CYREG_DW1_CH_STRUCT46_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298B94UL)
#define CYREG_DW1_CH_STRUCT46_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298B98UL)
#define CYREG_DW1_CH_STRUCT46_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40298B9CUL)
#define CYREG_DW1_CH_STRUCT46_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298BA0UL)
#define CYREG_DW1_CH_STRUCT46_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298BA4UL)
#define CYREG_DW1_CH_STRUCT46_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298BA8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT47)
  */
#define CYREG_DW1_CH_STRUCT47_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298BC0UL)
#define CYREG_DW1_CH_STRUCT47_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298BC4UL)
#define CYREG_DW1_CH_STRUCT47_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298BC8UL)
#define CYREG_DW1_CH_STRUCT47_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40298BCCUL)
#define CYREG_DW1_CH_STRUCT47_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298BD0UL)
#define CYREG_DW1_CH_STRUCT47_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298BD4UL)
#define CYREG_DW1_CH_STRUCT47_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298BD8UL)
#define CYREG_DW1_CH_STRUCT47_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40298BDCUL)
#define CYREG_DW1_CH_STRUCT47_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298BE0UL)
#define CYREG_DW1_CH_STRUCT47_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298BE4UL)
#define CYREG_DW1_CH_STRUCT47_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298BE8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT48)
  */
#define CYREG_DW1_CH_STRUCT48_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298C00UL)
#define CYREG_DW1_CH_STRUCT48_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298C04UL)
#define CYREG_DW1_CH_STRUCT48_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298C08UL)
#define CYREG_DW1_CH_STRUCT48_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40298C0CUL)
#define CYREG_DW1_CH_STRUCT48_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298C10UL)
#define CYREG_DW1_CH_STRUCT48_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298C14UL)
#define CYREG_DW1_CH_STRUCT48_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298C18UL)
#define CYREG_DW1_CH_STRUCT48_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40298C1CUL)
#define CYREG_DW1_CH_STRUCT48_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298C20UL)
#define CYREG_DW1_CH_STRUCT48_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298C24UL)
#define CYREG_DW1_CH_STRUCT48_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298C28UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT49)
  */
#define CYREG_DW1_CH_STRUCT49_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298C40UL)
#define CYREG_DW1_CH_STRUCT49_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298C44UL)
#define CYREG_DW1_CH_STRUCT49_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298C48UL)
#define CYREG_DW1_CH_STRUCT49_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40298C4CUL)
#define CYREG_DW1_CH_STRUCT49_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298C50UL)
#define CYREG_DW1_CH_STRUCT49_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298C54UL)
#define CYREG_DW1_CH_STRUCT49_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298C58UL)
#define CYREG_DW1_CH_STRUCT49_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40298C5CUL)
#define CYREG_DW1_CH_STRUCT49_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298C60UL)
#define CYREG_DW1_CH_STRUCT49_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298C64UL)
#define CYREG_DW1_CH_STRUCT49_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298C68UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT50)
  */
#define CYREG_DW1_CH_STRUCT50_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298C80UL)
#define CYREG_DW1_CH_STRUCT50_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298C84UL)
#define CYREG_DW1_CH_STRUCT50_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298C88UL)
#define CYREG_DW1_CH_STRUCT50_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40298C8CUL)
#define CYREG_DW1_CH_STRUCT50_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298C90UL)
#define CYREG_DW1_CH_STRUCT50_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298C94UL)
#define CYREG_DW1_CH_STRUCT50_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298C98UL)
#define CYREG_DW1_CH_STRUCT50_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40298C9CUL)
#define CYREG_DW1_CH_STRUCT50_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298CA0UL)
#define CYREG_DW1_CH_STRUCT50_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298CA4UL)
#define CYREG_DW1_CH_STRUCT50_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298CA8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT51)
  */
#define CYREG_DW1_CH_STRUCT51_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298CC0UL)
#define CYREG_DW1_CH_STRUCT51_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298CC4UL)
#define CYREG_DW1_CH_STRUCT51_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298CC8UL)
#define CYREG_DW1_CH_STRUCT51_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40298CCCUL)
#define CYREG_DW1_CH_STRUCT51_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298CD0UL)
#define CYREG_DW1_CH_STRUCT51_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298CD4UL)
#define CYREG_DW1_CH_STRUCT51_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298CD8UL)
#define CYREG_DW1_CH_STRUCT51_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40298CDCUL)
#define CYREG_DW1_CH_STRUCT51_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298CE0UL)
#define CYREG_DW1_CH_STRUCT51_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298CE4UL)
#define CYREG_DW1_CH_STRUCT51_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298CE8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT52)
  */
#define CYREG_DW1_CH_STRUCT52_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298D00UL)
#define CYREG_DW1_CH_STRUCT52_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298D04UL)
#define CYREG_DW1_CH_STRUCT52_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298D08UL)
#define CYREG_DW1_CH_STRUCT52_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40298D0CUL)
#define CYREG_DW1_CH_STRUCT52_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298D10UL)
#define CYREG_DW1_CH_STRUCT52_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298D14UL)
#define CYREG_DW1_CH_STRUCT52_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298D18UL)
#define CYREG_DW1_CH_STRUCT52_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40298D1CUL)
#define CYREG_DW1_CH_STRUCT52_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298D20UL)
#define CYREG_DW1_CH_STRUCT52_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298D24UL)
#define CYREG_DW1_CH_STRUCT52_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298D28UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT53)
  */
#define CYREG_DW1_CH_STRUCT53_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298D40UL)
#define CYREG_DW1_CH_STRUCT53_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298D44UL)
#define CYREG_DW1_CH_STRUCT53_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298D48UL)
#define CYREG_DW1_CH_STRUCT53_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40298D4CUL)
#define CYREG_DW1_CH_STRUCT53_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298D50UL)
#define CYREG_DW1_CH_STRUCT53_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298D54UL)
#define CYREG_DW1_CH_STRUCT53_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298D58UL)
#define CYREG_DW1_CH_STRUCT53_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40298D5CUL)
#define CYREG_DW1_CH_STRUCT53_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298D60UL)
#define CYREG_DW1_CH_STRUCT53_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298D64UL)
#define CYREG_DW1_CH_STRUCT53_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298D68UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT54)
  */
#define CYREG_DW1_CH_STRUCT54_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298D80UL)
#define CYREG_DW1_CH_STRUCT54_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298D84UL)
#define CYREG_DW1_CH_STRUCT54_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298D88UL)
#define CYREG_DW1_CH_STRUCT54_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40298D8CUL)
#define CYREG_DW1_CH_STRUCT54_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298D90UL)
#define CYREG_DW1_CH_STRUCT54_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298D94UL)
#define CYREG_DW1_CH_STRUCT54_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298D98UL)
#define CYREG_DW1_CH_STRUCT54_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40298D9CUL)
#define CYREG_DW1_CH_STRUCT54_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298DA0UL)
#define CYREG_DW1_CH_STRUCT54_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298DA4UL)
#define CYREG_DW1_CH_STRUCT54_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298DA8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT55)
  */
#define CYREG_DW1_CH_STRUCT55_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298DC0UL)
#define CYREG_DW1_CH_STRUCT55_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298DC4UL)
#define CYREG_DW1_CH_STRUCT55_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298DC8UL)
#define CYREG_DW1_CH_STRUCT55_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40298DCCUL)
#define CYREG_DW1_CH_STRUCT55_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298DD0UL)
#define CYREG_DW1_CH_STRUCT55_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298DD4UL)
#define CYREG_DW1_CH_STRUCT55_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298DD8UL)
#define CYREG_DW1_CH_STRUCT55_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40298DDCUL)
#define CYREG_DW1_CH_STRUCT55_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298DE0UL)
#define CYREG_DW1_CH_STRUCT55_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298DE4UL)
#define CYREG_DW1_CH_STRUCT55_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298DE8UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT56)
  */
#define CYREG_DW1_CH_STRUCT56_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298E00UL)
#define CYREG_DW1_CH_STRUCT56_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298E04UL)
#define CYREG_DW1_CH_STRUCT56_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298E08UL)
#define CYREG_DW1_CH_STRUCT56_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40298E0CUL)
#define CYREG_DW1_CH_STRUCT56_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298E10UL)
#define CYREG_DW1_CH_STRUCT56_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298E14UL)
#define CYREG_DW1_CH_STRUCT56_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298E18UL)
#define CYREG_DW1_CH_STRUCT56_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40298E1CUL)
#define CYREG_DW1_CH_STRUCT56_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298E20UL)
#define CYREG_DW1_CH_STRUCT56_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298E24UL)
#define CYREG_DW1_CH_STRUCT56_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298E28UL)

/**
  * \brief DW channel structure (DW_CH_STRUCT57)
  */
#define CYREG_DW1_CH_STRUCT57_CH_CTL    ((volatile un_DW_CH_STRUCT_CH_CTL_t*) 0x40298E40UL)
#define CYREG_DW1_CH_STRUCT57_CH_STATUS ((volatile un_DW_CH_STRUCT_CH_STATUS_t*) 0x40298E44UL)
#define CYREG_DW1_CH_STRUCT57_CH_IDX    ((volatile un_DW_CH_STRUCT_CH_IDX_t*) 0x40298E48UL)
#define CYREG_DW1_CH_STRUCT57_CH_CURR_PTR ((volatile un_DW_CH_STRUCT_CH_CURR_PTR_t*) 0x40298E4CUL)
#define CYREG_DW1_CH_STRUCT57_INTR      ((volatile un_DW_CH_STRUCT_INTR_t*) 0x40298E50UL)
#define CYREG_DW1_CH_STRUCT57_INTR_SET  ((volatile un_DW_CH_STRUCT_INTR_SET_t*) 0x40298E54UL)
#define CYREG_DW1_CH_STRUCT57_INTR_MASK ((volatile un_DW_CH_STRUCT_INTR_MASK_t*) 0x40298E58UL)
#define CYREG_DW1_CH_STRUCT57_INTR_MASKED ((volatile un_DW_CH_STRUCT_INTR_MASKED_t*) 0x40298E5CUL)
#define CYREG_DW1_CH_STRUCT57_SRAM_DATA0 ((volatile un_DW_CH_STRUCT_SRAM_DATA0_t*) 0x40298E60UL)
#define CYREG_DW1_CH_STRUCT57_SRAM_DATA1 ((volatile un_DW_CH_STRUCT_SRAM_DATA1_t*) 0x40298E64UL)
#define CYREG_DW1_CH_STRUCT57_TR_CMD    ((volatile un_DW_CH_STRUCT_TR_CMD_t*) 0x40298E68UL)

/**
  * \brief Datawire Controller (DW0)
  */
#define CYREG_DW1_CTL0                  ((volatile un_DW_CTL_t*) 0x40290000UL)
#define CYREG_DW1_STATUS0               ((volatile un_DW_STATUS_t*) 0x40290004UL)
#define CYREG_DW1_ACT_DESCR_CTL0        ((volatile un_DW_ACT_DESCR_CTL_t*) 0x40290020UL)
#define CYREG_DW1_ACT_DESCR_SRC0        ((volatile un_DW_ACT_DESCR_SRC_t*) 0x40290024UL)
#define CYREG_DW1_ACT_DESCR_DST0        ((volatile un_DW_ACT_DESCR_DST_t*) 0x40290028UL)
#define CYREG_DW1_ACT_DESCR_X_CTL0      ((volatile un_DW_ACT_DESCR_X_CTL_t*) 0x40290030UL)
#define CYREG_DW1_ACT_DESCR_Y_CTL0      ((volatile un_DW_ACT_DESCR_Y_CTL_t*) 0x40290034UL)
#define CYREG_DW1_ACT_DESCR_NEXT_PTR0   ((volatile un_DW_ACT_DESCR_NEXT_PTR_t*) 0x40290038UL)
#define CYREG_DW1_ACT_SRC0              ((volatile un_DW_ACT_SRC_t*) 0x40290040UL)
#define CYREG_DW1_ACT_DST0              ((volatile un_DW_ACT_DST_t*) 0x40290044UL)
#define CYREG_DW1_ECC_CTL0              ((volatile un_DW_ECC_CTL_t*) 0x40290080UL)
#define CYREG_DW1_CRC_CTL0              ((volatile un_DW_CRC_CTL_t*) 0x40290100UL)
#define CYREG_DW1_CRC_DATA_CTL0         ((volatile un_DW_CRC_DATA_CTL_t*) 0x40290110UL)
#define CYREG_DW1_CRC_POL_CTL0          ((volatile un_DW_CRC_POL_CTL_t*) 0x40290120UL)
#define CYREG_DW1_CRC_LFSR_CTL0         ((volatile un_DW_CRC_LFSR_CTL_t*) 0x40290130UL)
#define CYREG_DW1_CRC_REM_CTL0          ((volatile un_DW_CRC_REM_CTL_t*) 0x40290140UL)
#define CYREG_DW1_CRC_REM_RESULT0       ((volatile un_DW_CRC_REM_RESULT_t*) 0x40290148UL)

#endif /* _CYREG_DW_H_ */


/* [] END OF FILE */
